440 lines
12 KiB
ArmAsm
440 lines
12 KiB
ArmAsm
/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
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*
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* Copyright (C) 2006 <davem@davemloft.net>
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*/
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.text
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.align 32
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sun4v_itlb_miss:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load UTSB reg into %g1. */
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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*/
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_itlb_4v
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nop
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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cmp %g2, %g6
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sethi %hi(_PAGE_EXEC), %g7
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_ITLB, %g3
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andcc %g3, %g7, %g0
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be,a,pn %xcc, tsb_do_fault
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mov FAULT_CODE_ITLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* I-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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* %g6: TAG TARGET (only "CTX << 48" part matters)
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*/
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sun4v_itlb_load:
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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srlx %g6, 48, %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_IMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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mov %g1, %o0 ! restore %o0
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mov %g2, %o1 ! restore %o1
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_miss:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load UTSB reg into %g1. */
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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*/
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_dtlb_4v
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nop
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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cmp %g2, %g6
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_ITLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* D-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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* %g6: TAG TARGET (only "CTX << 48" part matters)
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*/
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sun4v_dtlb_load:
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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srlx %g6, 48, %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_DMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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mov %g1, %o0 ! restore %o0
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mov %g2, %o1 ! restore %o1
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_prot:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g5
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rdpr %tl, %g1
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cmp %g1, 1
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bgu,pn %xcc, winfix_trampoline
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nop
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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/* Called from trap table with &trap_block[smp_processor_id()] in
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* %g5 and SCRATCHPAD_UTSBREG1 contents in %g1.
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*/
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sun4v_itsb_miss:
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ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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srlx %g4, 22, %g7
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sllx %g5, 48, %g6
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or %g6, %g7, %g6
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brz,pn %g5, kvmap_itlb_4v
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nop
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ba,pt %xcc, sun4v_tsb_miss_common
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mov FAULT_CODE_ITLB, %g3
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/* Called from trap table with &trap_block[smp_processor_id()] in
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* %g5 and SCRATCHPAD_UTSBREG1 contents in %g1.
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*/
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sun4v_dtsb_miss:
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ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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srlx %g4, 22, %g7
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sllx %g5, 48, %g6
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or %g6, %g7, %g6
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brz,pn %g5, kvmap_dtlb_4v
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nop
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mov FAULT_CODE_DTLB, %g3
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/* Create TSB pointer into %g1. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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sun4v_tsb_miss_common:
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and %g1, 0x7, %g2
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g2, %g7
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sub %g7, 1, %g7
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srlx %g4, PAGE_SHIFT, %g2
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and %g2, %g7, %g2
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sllx %g2, 4, %g2
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ba,pt %xcc, tsb_miss_page_table_walk
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add %g1, %g2, %g1
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/* Instruction Access Exception, tl0. */
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sun4v_iacc:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Instruction Access Exception, tl1. */
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sun4v_iacc_tl1:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Data Access Exception, tl0. */
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sun4v_dacc:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Data Access Exception, tl1. */
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sun4v_dacc_tl1:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Memory Address Unaligned. */
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sun4v_mna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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/* Window fixup? */
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rdpr %tl, %g2
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cmp %g2, 1
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bgu,pn %icc, winfix_mna
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rdpr %tpc, %g3
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_mna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Privileged Action. */
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sun4v_privact:
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_privact
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Unaligned ldd float, tl0. */
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sun4v_lddfmna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call handle_lddfmna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Unaligned std float, tl0. */
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sun4v_stdfmna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call handle_stdfmna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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#define BRANCH_ALWAYS 0x10680000
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#define NOP 0x01000000
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#define SUN4V_DO_PATCH(OLD, NEW) \
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sethi %hi(NEW), %g1; \
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or %g1, %lo(NEW), %g1; \
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sethi %hi(OLD), %g2; \
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or %g2, %lo(OLD), %g2; \
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sub %g1, %g2, %g1; \
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sethi %hi(BRANCH_ALWAYS), %g3; \
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srl %g1, 2, %g1; \
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or %g3, %lo(BRANCH_ALWAYS), %g3; \
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or %g3, %g1, %g3; \
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stw %g3, [%g2]; \
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sethi %hi(NOP), %g3; \
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or %g3, %lo(NOP), %g3; \
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stw %g3, [%g2 + 0x4]; \
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flush %g2;
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.globl sun4v_patch_tlb_handlers
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.type sun4v_patch_tlb_handlers,#function
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sun4v_patch_tlb_handlers:
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SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
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SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
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SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
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SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
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SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
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SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
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SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
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SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
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SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
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SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
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SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
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SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
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SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
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SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
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SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
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|
retl
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nop
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.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
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