d5d14ed6f2
This change introduces new flags for the hv_install_context() API that passes a page table pointer to the hypervisor. Clients can explicitly request 4K, 16K, or 64K small pages when they install a new context. In practice, the page size is fixed at kernel compile time and the same size is always requested every time a new page table is installed. The <hv/hypervisor.h> header changes so that it provides more abstract macros for managing "page" things like PFNs and page tables. For example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old HV_PAGE_SIZE_SMALL. The various PFN routines have been eliminated and only PA- or PTFN-based ones remain (since PTFNs are always expressed in fixed 2KB "page" size). The page-table management macros are renamed with a leading underscore and take page-size arguments with the presumption that clients will use those macros in some single place to provide the "real" macros they will use themselves. I happened to notice the old hv_set_caching() API was totally broken (it assumed 4KB pages) so I changed it so it would nominally work correctly with other page sizes. Tag modules with the page size so you can't load a module built with a conflicting page size. (And add a test for SMP while we're at it.) Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef _ASM_TILE_PGTABLE_32_H
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#define _ASM_TILE_PGTABLE_32_H
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/*
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* The level-1 index is defined by the huge page size. A PGD is composed
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* of PTRS_PER_PGD pgd_t's and is the top level of the page table.
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*/
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#define PGDIR_SHIFT HPAGE_SHIFT
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#define PGDIR_SIZE HPAGE_SIZE
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD _HV_L1_ENTRIES(HPAGE_SHIFT)
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#define PGD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
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#define SIZEOF_PGD _HV_L1_SIZE(HPAGE_SHIFT)
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/*
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* The level-2 index is defined by the difference between the huge
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* page size and the normal page size. A PTE is composed of
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* PTRS_PER_PTE pte_t's and is the bottom level of the page table.
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* Note that the hypervisor docs use PTE for what we call pte_t, so
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* this nomenclature is somewhat confusing.
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*/
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#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
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#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
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#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
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#ifndef __ASSEMBLY__
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/*
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* Right now we initialize only a single pte table. It can be extended
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* easily, subsequent pte tables have to be allocated in one physical
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* chunk of RAM.
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*
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* HOWEVER, if we are using an allocation scheme with slop after the
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* end of the page table (e.g. where our L2 page tables are 2KB but
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* our pages are 64KB and we are allocating via the page allocator)
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* we can't extend it easily.
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*/
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#define LAST_PKMAP PTRS_PER_PTE
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#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE*LAST_PKMAP) & PGDIR_MASK)
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#ifdef CONFIG_HIGHMEM
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# define __VMAPPING_END (PKMAP_BASE & ~(HPAGE_SIZE-1))
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#else
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# define __VMAPPING_END (FIXADDR_START & ~(HPAGE_SIZE-1))
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#endif
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#ifdef CONFIG_HUGEVMAP
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#define HUGE_VMAP_END __VMAPPING_END
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#define HUGE_VMAP_BASE (HUGE_VMAP_END - CONFIG_NR_HUGE_VMAPS * HPAGE_SIZE)
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#define _VMALLOC_END HUGE_VMAP_BASE
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#else
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#define _VMALLOC_END __VMAPPING_END
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#endif
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/*
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* Align the vmalloc area to an L2 page table, and leave a guard page
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* at the beginning and end. The vmalloc code also puts in an internal
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* guard page between each allocation.
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*/
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#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
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extern unsigned long VMALLOC_RESERVE /* = CONFIG_VMALLOC_RESERVE */;
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#define _VMALLOC_START (_VMALLOC_END - VMALLOC_RESERVE)
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#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
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/* This is the maximum possible amount of lowmem. */
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#define MAXMEM (_VMALLOC_START - PAGE_OFFSET)
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/* We have no pmd or pud since we are strictly a two-level page table */
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#include <asm-generic/pgtable-nopmd.h>
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/* We don't define any pgds for these addresses. */
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static inline int pgd_addr_invalid(unsigned long addr)
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{
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return addr >= MEM_HV_INTRPT;
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}
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/*
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* Provide versions of these routines that can be used safely when
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* the hypervisor may be asynchronously modifying dirty/accessed bits.
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* ptep_get_and_clear() matches the generic one but we provide it to
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* be parallel with the 64-bit code.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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extern int ptep_test_and_clear_young(struct vm_area_struct *,
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unsigned long addr, pte_t *);
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extern void ptep_set_wrprotect(struct mm_struct *,
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unsigned long addr, pte_t *);
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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pte_clear(_mm, addr, ptep);
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return pte;
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}
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/*
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* pmds are wrappers around pgds, which are the same as ptes.
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* It's often convenient to "cast" back and forth and use the pte methods,
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* which are the methods supplied by the hypervisor.
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*/
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#define pmd_pte(pmd) ((pmd).pud.pgd)
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#define pmdp_ptep(pmdp) (&(pmdp)->pud.pgd)
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#define pte_pmd(pte) ((pmd_t){ { (pte) } })
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_TILE_PGTABLE_32_H */
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