8d053c79f2
If the EHCI debug port is initialized and in use, the EHCI host controller driver must follow two rules. 1) If the EHCI host driver issues a controller reset, the debug controller driver re-initialization must get called after the reset is completed. 2) The EHCI host driver should ignore any requests to the physical EHCI debug port when the EHCI debug port is in use. The code to check for the debug port was moved from ehci_pci_reinit() to ehci_pci_setup because it must get called prior to ehci_reset() which will clear the debug port registers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: dbrownell@users.sourceforge.net Cc: Ingo Molnar <mingo@elte.hu> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
958 lines
22 KiB
C
958 lines
22 KiB
C
/*
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* Standalone EHCI usb debug driver
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*
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* Originally written by:
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* Eric W. Biederman" <ebiederm@xmission.com> and
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* Yinghai Lu <yhlu.kernel@gmail.com>
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*
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* Changes for early/late printk and HW errata:
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* Jason Wessel <jason.wessel@windriver.com>
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* Copyright (C) 2009 Wind River Systems, Inc.
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*
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*/
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#include <linux/console.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/pci_regs.h>
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#include <linux/pci_ids.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/ehci_def.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/pci-direct.h>
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#include <asm/fixmap.h>
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/* The code here is intended to talk directly to the EHCI debug port
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* and does not require that you have any kind of USB host controller
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* drivers or USB device drivers compiled into the kernel.
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*
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* If you make a change to anything in here, the following test cases
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* need to pass where a USB debug device works in the following
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* configurations.
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*
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* 1. boot args: earlyprintk=dbgp
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* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
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* o kernel compiled with CONFIG_USB_EHCI_HCD=y
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* 2. boot args: earlyprintk=dbgp,keep
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* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
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* o kernel compiled with CONFIG_USB_EHCI_HCD=y
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* 3. boot args: earlyprintk=dbgp console=ttyUSB0
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* o kernel has CONFIG_USB_EHCI_HCD=y and
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* CONFIG_USB_SERIAL_DEBUG=y
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* 4. boot args: earlyprintk=vga,dbgp
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* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
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* o kernel compiled with CONFIG_USB_EHCI_HCD=y
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*
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* For the 4th configuration you can turn on or off the DBGP_DEBUG
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* such that you can debug the dbgp device's driver code.
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*/
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static int dbgp_phys_port = 1;
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static struct ehci_caps __iomem *ehci_caps;
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static struct ehci_regs __iomem *ehci_regs;
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static struct ehci_dbg_port __iomem *ehci_debug;
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static int dbgp_not_safe; /* Cannot use debug device during ehci reset */
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static unsigned int dbgp_endpoint_out;
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struct ehci_dev {
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u32 bus;
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u32 slot;
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u32 func;
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};
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static struct ehci_dev ehci_dev;
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#define USB_DEBUG_DEVNUM 127
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#define DBGP_DATA_TOGGLE 0x8800
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#ifdef DBGP_DEBUG
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#define dbgp_printk printk
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static void dbgp_ehci_status(char *str)
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{
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if (!ehci_debug)
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return;
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dbgp_printk("dbgp: %s\n", str);
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dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control));
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dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command));
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dbgp_printk(" ehci conf flg: %08x\n",
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readl(&ehci_regs->configured_flag));
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dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status));
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dbgp_printk(" ehci portsc : %08x\n",
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readl(&ehci_regs->port_status[dbgp_phys_port - 1]));
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}
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#else
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static inline void dbgp_ehci_status(char *str) { }
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static inline void dbgp_printk(const char *fmt, ...) { }
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#endif
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static inline u32 dbgp_pid_update(u32 x, u32 tok)
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{
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return ((x ^ DBGP_DATA_TOGGLE) & 0xffff00) | (tok & 0xff);
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}
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static inline u32 dbgp_len_update(u32 x, u32 len)
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{
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return (x & ~0x0f) | (len & 0x0f);
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}
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/*
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* USB Packet IDs (PIDs)
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*/
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/* token */
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#define USB_PID_OUT 0xe1
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#define USB_PID_IN 0x69
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#define USB_PID_SOF 0xa5
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#define USB_PID_SETUP 0x2d
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/* handshake */
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#define USB_PID_ACK 0xd2
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#define USB_PID_NAK 0x5a
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#define USB_PID_STALL 0x1e
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#define USB_PID_NYET 0x96
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/* data */
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#define USB_PID_DATA0 0xc3
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#define USB_PID_DATA1 0x4b
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#define USB_PID_DATA2 0x87
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#define USB_PID_MDATA 0x0f
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/* Special */
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#define USB_PID_PREAMBLE 0x3c
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#define USB_PID_ERR 0x3c
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#define USB_PID_SPLIT 0x78
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#define USB_PID_PING 0xb4
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#define USB_PID_UNDEF_0 0xf0
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#define USB_PID_DATA_TOGGLE 0x88
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#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
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#define PCI_CAP_ID_EHCI_DEBUG 0xa
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#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
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#define HUB_SHORT_RESET_TIME 10
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#define HUB_LONG_RESET_TIME 200
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#define HUB_RESET_TIMEOUT 500
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#define DBGP_MAX_PACKET 8
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#define DBGP_TIMEOUT (250 * 1000)
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static int dbgp_wait_until_complete(void)
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{
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u32 ctrl;
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int loop = DBGP_TIMEOUT;
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do {
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ctrl = readl(&ehci_debug->control);
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/* Stop when the transaction is finished */
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if (ctrl & DBGP_DONE)
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break;
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udelay(1);
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} while (--loop > 0);
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if (!loop)
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return -DBGP_TIMEOUT;
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/*
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* Now that we have observed the completed transaction,
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* clear the done bit.
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*/
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writel(ctrl | DBGP_DONE, &ehci_debug->control);
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return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
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}
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static inline void dbgp_mdelay(int ms)
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{
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int i;
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while (ms--) {
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for (i = 0; i < 1000; i++)
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outb(0x1, 0x80);
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}
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}
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static void dbgp_breath(void)
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{
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/* Sleep to give the debug port a chance to breathe */
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}
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static int dbgp_wait_until_done(unsigned ctrl)
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{
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u32 pids, lpid;
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int ret;
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int loop = 3;
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retry:
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writel(ctrl | DBGP_GO, &ehci_debug->control);
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ret = dbgp_wait_until_complete();
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pids = readl(&ehci_debug->pids);
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lpid = DBGP_PID_GET(pids);
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if (ret < 0) {
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/* A -DBGP_TIMEOUT failure here means the device has
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* failed, perhaps because it was unplugged, in which
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* case we do not want to hang the system so the dbgp
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* will be marked as unsafe to use. EHCI reset is the
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* only way to recover if you unplug the dbgp device.
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*/
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if (ret == -DBGP_TIMEOUT && !dbgp_not_safe)
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dbgp_not_safe = 1;
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return ret;
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}
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/*
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* If the port is getting full or it has dropped data
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* start pacing ourselves, not necessary but it's friendly.
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*/
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if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
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dbgp_breath();
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/* If I get a NACK reissue the transmission */
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if (lpid == USB_PID_NAK) {
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if (--loop > 0)
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goto retry;
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}
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return ret;
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}
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static inline void dbgp_set_data(const void *buf, int size)
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{
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const unsigned char *bytes = buf;
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u32 lo, hi;
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int i;
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lo = hi = 0;
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for (i = 0; i < 4 && i < size; i++)
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lo |= bytes[i] << (8*i);
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for (; i < 8 && i < size; i++)
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hi |= bytes[i] << (8*(i - 4));
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writel(lo, &ehci_debug->data03);
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writel(hi, &ehci_debug->data47);
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}
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static inline void dbgp_get_data(void *buf, int size)
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{
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unsigned char *bytes = buf;
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u32 lo, hi;
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int i;
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lo = readl(&ehci_debug->data03);
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hi = readl(&ehci_debug->data47);
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for (i = 0; i < 4 && i < size; i++)
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bytes[i] = (lo >> (8*i)) & 0xff;
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for (; i < 8 && i < size; i++)
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bytes[i] = (hi >> (8*(i - 4))) & 0xff;
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}
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static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
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const char *bytes, int size)
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{
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u32 pids, addr, ctrl;
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int ret;
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if (size > DBGP_MAX_PACKET)
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return -1;
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addr = DBGP_EPADDR(devnum, endpoint);
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pids = readl(&ehci_debug->pids);
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pids = dbgp_pid_update(pids, USB_PID_OUT);
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ctrl = readl(&ehci_debug->control);
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ctrl = dbgp_len_update(ctrl, size);
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ctrl |= DBGP_OUT;
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ctrl |= DBGP_GO;
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dbgp_set_data(bytes, size);
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writel(addr, &ehci_debug->address);
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writel(pids, &ehci_debug->pids);
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ret = dbgp_wait_until_done(ctrl);
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if (ret < 0)
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return ret;
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return ret;
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}
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static int dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
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int size)
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{
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u32 pids, addr, ctrl;
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int ret;
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if (size > DBGP_MAX_PACKET)
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return -1;
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addr = DBGP_EPADDR(devnum, endpoint);
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pids = readl(&ehci_debug->pids);
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pids = dbgp_pid_update(pids, USB_PID_IN);
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ctrl = readl(&ehci_debug->control);
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ctrl = dbgp_len_update(ctrl, size);
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ctrl &= ~DBGP_OUT;
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ctrl |= DBGP_GO;
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writel(addr, &ehci_debug->address);
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writel(pids, &ehci_debug->pids);
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ret = dbgp_wait_until_done(ctrl);
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if (ret < 0)
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return ret;
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if (size > ret)
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size = ret;
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dbgp_get_data(data, size);
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return ret;
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}
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static int dbgp_control_msg(unsigned devnum, int requesttype,
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int request, int value, int index, void *data, int size)
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{
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u32 pids, addr, ctrl;
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struct usb_ctrlrequest req;
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int read;
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int ret;
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read = (requesttype & USB_DIR_IN) != 0;
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if (size > (read ? DBGP_MAX_PACKET:0))
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return -1;
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/* Compute the control message */
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req.bRequestType = requesttype;
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req.bRequest = request;
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req.wValue = cpu_to_le16(value);
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req.wIndex = cpu_to_le16(index);
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req.wLength = cpu_to_le16(size);
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pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
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addr = DBGP_EPADDR(devnum, 0);
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ctrl = readl(&ehci_debug->control);
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ctrl = dbgp_len_update(ctrl, sizeof(req));
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ctrl |= DBGP_OUT;
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ctrl |= DBGP_GO;
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/* Send the setup message */
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dbgp_set_data(&req, sizeof(req));
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writel(addr, &ehci_debug->address);
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writel(pids, &ehci_debug->pids);
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ret = dbgp_wait_until_done(ctrl);
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if (ret < 0)
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return ret;
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/* Read the result */
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return dbgp_bulk_read(devnum, 0, data, size);
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}
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/* Find a PCI capability */
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static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
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{
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u8 pos;
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int bytes;
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if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
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PCI_STATUS_CAP_LIST))
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return 0;
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pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
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for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
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u8 id;
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pos &= ~3;
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id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos = read_pci_config_byte(num, slot, func,
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pos+PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
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{
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u32 class;
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class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
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if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
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return 0;
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return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
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}
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static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
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{
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u32 bus, slot, func;
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for (bus = 0; bus < 256; bus++) {
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for (slot = 0; slot < 32; slot++) {
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for (func = 0; func < 8; func++) {
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unsigned cap;
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cap = __find_dbgp(bus, slot, func);
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if (!cap)
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continue;
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if (ehci_num-- != 0)
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continue;
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*rbus = bus;
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*rslot = slot;
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*rfunc = func;
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return cap;
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}
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}
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}
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return 0;
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}
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static int dbgp_ehci_startup(void)
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{
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u32 ctrl, cmd, status;
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int loop;
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/* Claim ownership, but do not enable yet */
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ctrl = readl(&ehci_debug->control);
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ctrl |= DBGP_OWNER;
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ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
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writel(ctrl, &ehci_debug->control);
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udelay(1);
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dbgp_ehci_status("EHCI startup");
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/* Start the ehci running */
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cmd = readl(&ehci_regs->command);
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cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
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cmd |= CMD_RUN;
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writel(cmd, &ehci_regs->command);
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/* Ensure everything is routed to the EHCI */
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writel(FLAG_CF, &ehci_regs->configured_flag);
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/* Wait until the controller is no longer halted */
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loop = 10;
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do {
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status = readl(&ehci_regs->status);
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if (!(status & STS_HALT))
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break;
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udelay(1);
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} while (--loop > 0);
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if (!loop) {
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dbgp_printk("ehci can not be started\n");
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return -ENODEV;
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}
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dbgp_printk("ehci started\n");
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return 0;
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}
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static int dbgp_ehci_controller_reset(void)
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{
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int loop = 250 * 1000;
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u32 cmd;
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/* Reset the EHCI controller */
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cmd = readl(&ehci_regs->command);
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cmd |= CMD_RESET;
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writel(cmd, &ehci_regs->command);
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do {
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cmd = readl(&ehci_regs->command);
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} while ((cmd & CMD_RESET) && (--loop > 0));
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if (!loop) {
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dbgp_printk("can not reset ehci\n");
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return -1;
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}
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dbgp_ehci_status("ehci reset done");
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return 0;
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}
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static int ehci_wait_for_port(int port);
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/* Return 0 on success
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* Return -ENODEV for any general failure
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* Return -EIO if wait for port fails
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*/
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int dbgp_external_startup(void)
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{
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int devnum;
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struct usb_debug_descriptor dbgp_desc;
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int ret;
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u32 ctrl, portsc;
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int dbg_port = dbgp_phys_port;
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int tries = 3;
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ret = dbgp_ehci_startup();
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if (ret)
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return ret;
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/* Wait for a device to show up in the debug port */
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ret = ehci_wait_for_port(dbg_port);
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if (ret < 0) {
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portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
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dbgp_printk("No device found in debug port\n");
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return -EIO;
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}
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dbgp_ehci_status("wait for port done");
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/* Enable the debug port */
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ctrl = readl(&ehci_debug->control);
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ctrl |= DBGP_CLAIM;
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writel(ctrl, &ehci_debug->control);
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ctrl = readl(&ehci_debug->control);
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if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
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dbgp_printk("No device in debug port\n");
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writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
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return -ENODEV;
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}
|
|
dbgp_ehci_status("debug ported enabled");
|
|
|
|
/* Completely transfer the debug device to the debug controller */
|
|
portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
|
|
portsc &= ~PORT_PE;
|
|
writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
|
|
|
|
dbgp_mdelay(100);
|
|
|
|
try_again:
|
|
/* Find the debug device and make it device number 127 */
|
|
for (devnum = 0; devnum <= 127; devnum++) {
|
|
ret = dbgp_control_msg(devnum,
|
|
USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
|
USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
|
|
&dbgp_desc, sizeof(dbgp_desc));
|
|
if (ret > 0)
|
|
break;
|
|
}
|
|
if (devnum > 127) {
|
|
dbgp_printk("Could not find attached debug device\n");
|
|
goto err;
|
|
}
|
|
if (ret < 0) {
|
|
dbgp_printk("Attached device is not a debug device\n");
|
|
goto err;
|
|
}
|
|
dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
|
|
|
|
/* Move the device to 127 if it isn't already there */
|
|
if (devnum != USB_DEBUG_DEVNUM) {
|
|
ret = dbgp_control_msg(devnum,
|
|
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
|
USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
|
|
if (ret < 0) {
|
|
dbgp_printk("Could not move attached device to %d\n",
|
|
USB_DEBUG_DEVNUM);
|
|
goto err;
|
|
}
|
|
devnum = USB_DEBUG_DEVNUM;
|
|
dbgp_printk("debug device renamed to 127\n");
|
|
}
|
|
|
|
/* Enable the debug interface */
|
|
ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
|
|
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
|
|
USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
|
|
if (ret < 0) {
|
|
dbgp_printk(" Could not enable the debug device\n");
|
|
goto err;
|
|
}
|
|
dbgp_printk("debug interface enabled\n");
|
|
/* Perform a small write to get the even/odd data state in sync
|
|
*/
|
|
ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
|
|
if (ret < 0) {
|
|
dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
|
|
goto err;
|
|
}
|
|
dbgp_printk("small write doned\n");
|
|
dbgp_not_safe = 0;
|
|
|
|
return 0;
|
|
err:
|
|
if (tries--)
|
|
goto try_again;
|
|
return -ENODEV;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dbgp_external_startup);
|
|
|
|
static int __init ehci_reset_port(int port)
|
|
{
|
|
u32 portsc;
|
|
u32 delay_time, delay;
|
|
int loop;
|
|
|
|
dbgp_ehci_status("reset port");
|
|
/* Reset the usb debug port */
|
|
portsc = readl(&ehci_regs->port_status[port - 1]);
|
|
portsc &= ~PORT_PE;
|
|
portsc |= PORT_RESET;
|
|
writel(portsc, &ehci_regs->port_status[port - 1]);
|
|
|
|
delay = HUB_ROOT_RESET_TIME;
|
|
for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
|
|
delay_time += delay) {
|
|
dbgp_mdelay(delay);
|
|
portsc = readl(&ehci_regs->port_status[port - 1]);
|
|
if (!(portsc & PORT_RESET))
|
|
break;
|
|
}
|
|
if (portsc & PORT_RESET) {
|
|
/* force reset to complete */
|
|
loop = 100 * 1000;
|
|
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
|
|
&ehci_regs->port_status[port - 1]);
|
|
do {
|
|
udelay(1);
|
|
portsc = readl(&ehci_regs->port_status[port-1]);
|
|
} while ((portsc & PORT_RESET) && (--loop > 0));
|
|
}
|
|
|
|
/* Device went away? */
|
|
if (!(portsc & PORT_CONNECT))
|
|
return -ENOTCONN;
|
|
|
|
/* bomb out completely if something weird happend */
|
|
if ((portsc & PORT_CSC))
|
|
return -EINVAL;
|
|
|
|
/* If we've finished resetting, then break out of the loop */
|
|
if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
|
|
return 0;
|
|
return -EBUSY;
|
|
}
|
|
|
|
static int ehci_wait_for_port(int port)
|
|
{
|
|
u32 status;
|
|
int ret, reps;
|
|
|
|
for (reps = 0; reps < 300; reps++) {
|
|
status = readl(&ehci_regs->status);
|
|
if (status & STS_PCD)
|
|
break;
|
|
dbgp_mdelay(1);
|
|
}
|
|
ret = ehci_reset_port(port);
|
|
if (ret == 0)
|
|
return 0;
|
|
return -ENOTCONN;
|
|
}
|
|
|
|
typedef void (*set_debug_port_t)(int port);
|
|
|
|
static void __init default_set_debug_port(int port)
|
|
{
|
|
}
|
|
|
|
static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
|
|
|
|
static void __init nvidia_set_debug_port(int port)
|
|
{
|
|
u32 dword;
|
|
dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
|
|
0x74);
|
|
dword &= ~(0x0f<<12);
|
|
dword |= ((port & 0x0f)<<12);
|
|
write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
|
|
dword);
|
|
dbgp_printk("set debug port to %d\n", port);
|
|
}
|
|
|
|
static void __init detect_set_debug_port(void)
|
|
{
|
|
u32 vendorid;
|
|
|
|
vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
|
|
0x00);
|
|
|
|
if ((vendorid & 0xffff) == 0x10de) {
|
|
dbgp_printk("using nvidia set_debug_port\n");
|
|
set_debug_port = nvidia_set_debug_port;
|
|
}
|
|
}
|
|
|
|
/* The code in early_ehci_bios_handoff() is derived from the usb pci
|
|
* quirk initialization, but altered so as to use the early PCI
|
|
* routines. */
|
|
#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
|
|
#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
|
|
static void __init early_ehci_bios_handoff(void)
|
|
{
|
|
u32 hcc_params = readl(&ehci_caps->hcc_params);
|
|
int offset = (hcc_params >> 8) & 0xff;
|
|
u32 cap;
|
|
int msec;
|
|
|
|
if (!offset)
|
|
return;
|
|
|
|
cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
|
|
ehci_dev.func, offset);
|
|
dbgp_printk("dbgp: ehci BIOS state %08x\n", cap);
|
|
|
|
if ((cap & 0xff) == 1 && (cap & EHCI_USBLEGSUP_BIOS)) {
|
|
dbgp_printk("dbgp: BIOS handoff\n");
|
|
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
|
|
ehci_dev.func, offset + 3, 1);
|
|
}
|
|
|
|
/* if boot firmware now owns EHCI, spin till it hands it over. */
|
|
msec = 1000;
|
|
while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
|
|
mdelay(10);
|
|
msec -= 10;
|
|
cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
|
|
ehci_dev.func, offset);
|
|
}
|
|
|
|
if (cap & EHCI_USBLEGSUP_BIOS) {
|
|
/* well, possibly buggy BIOS... try to shut it down,
|
|
* and hope nothing goes too wrong */
|
|
dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap);
|
|
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
|
|
ehci_dev.func, offset + 2, 0);
|
|
}
|
|
|
|
/* just in case, always disable EHCI SMIs */
|
|
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
|
|
offset + EHCI_USBLEGCTLSTS, 0);
|
|
}
|
|
|
|
static int __init ehci_setup(void)
|
|
{
|
|
u32 ctrl, portsc, hcs_params;
|
|
u32 debug_port, new_debug_port = 0, n_ports;
|
|
int ret, i;
|
|
int port_map_tried;
|
|
int playtimes = 3;
|
|
|
|
early_ehci_bios_handoff();
|
|
|
|
try_next_time:
|
|
port_map_tried = 0;
|
|
|
|
try_next_port:
|
|
|
|
hcs_params = readl(&ehci_caps->hcs_params);
|
|
debug_port = HCS_DEBUG_PORT(hcs_params);
|
|
dbgp_phys_port = debug_port;
|
|
n_ports = HCS_N_PORTS(hcs_params);
|
|
|
|
dbgp_printk("debug_port: %d\n", debug_port);
|
|
dbgp_printk("n_ports: %d\n", n_ports);
|
|
dbgp_ehci_status("");
|
|
|
|
for (i = 1; i <= n_ports; i++) {
|
|
portsc = readl(&ehci_regs->port_status[i-1]);
|
|
dbgp_printk("portstatus%d: %08x\n", i, portsc);
|
|
}
|
|
|
|
if (port_map_tried && (new_debug_port != debug_port)) {
|
|
if (--playtimes) {
|
|
set_debug_port(new_debug_port);
|
|
goto try_next_time;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
/* Only reset the controller if it is not already in the
|
|
* configured state */
|
|
if (!(readl(&ehci_regs->configured_flag) & FLAG_CF)) {
|
|
if (dbgp_ehci_controller_reset() != 0)
|
|
return -1;
|
|
} else {
|
|
dbgp_ehci_status("ehci skip - already configured");
|
|
}
|
|
|
|
ret = dbgp_external_startup();
|
|
if (ret == -EIO)
|
|
goto next_debug_port;
|
|
|
|
if (ret < 0) {
|
|
/* Things didn't work so remove my claim */
|
|
ctrl = readl(&ehci_debug->control);
|
|
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
|
|
writel(ctrl, &ehci_debug->control);
|
|
return -1;
|
|
}
|
|
return 0;
|
|
|
|
next_debug_port:
|
|
port_map_tried |= (1<<(debug_port - 1));
|
|
new_debug_port = ((debug_port-1+1)%n_ports) + 1;
|
|
if (port_map_tried != ((1<<n_ports) - 1)) {
|
|
set_debug_port(new_debug_port);
|
|
goto try_next_port;
|
|
}
|
|
if (--playtimes) {
|
|
set_debug_port(new_debug_port);
|
|
goto try_next_time;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
int __init early_dbgp_init(char *s)
|
|
{
|
|
u32 debug_port, bar, offset;
|
|
u32 bus, slot, func, cap;
|
|
void __iomem *ehci_bar;
|
|
u32 dbgp_num;
|
|
u32 bar_val;
|
|
char *e;
|
|
int ret;
|
|
u8 byte;
|
|
|
|
if (!early_pci_allowed())
|
|
return -1;
|
|
|
|
dbgp_num = 0;
|
|
if (*s)
|
|
dbgp_num = simple_strtoul(s, &e, 10);
|
|
dbgp_printk("dbgp_num: %d\n", dbgp_num);
|
|
|
|
cap = find_dbgp(dbgp_num, &bus, &slot, &func);
|
|
if (!cap)
|
|
return -1;
|
|
|
|
dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
|
|
func);
|
|
|
|
debug_port = read_pci_config(bus, slot, func, cap);
|
|
bar = (debug_port >> 29) & 0x7;
|
|
bar = (bar * 4) + 0xc;
|
|
offset = (debug_port >> 16) & 0xfff;
|
|
dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
|
|
if (bar != PCI_BASE_ADDRESS_0) {
|
|
dbgp_printk("only debug ports on bar 1 handled.\n");
|
|
|
|
return -1;
|
|
}
|
|
|
|
bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
|
|
dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
|
|
if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
|
|
dbgp_printk("only simple 32bit mmio bars supported\n");
|
|
|
|
return -1;
|
|
}
|
|
|
|
/* double check if the mem space is enabled */
|
|
byte = read_pci_config_byte(bus, slot, func, 0x04);
|
|
if (!(byte & 0x2)) {
|
|
byte |= 0x02;
|
|
write_pci_config_byte(bus, slot, func, 0x04, byte);
|
|
dbgp_printk("mmio for ehci enabled\n");
|
|
}
|
|
|
|
/*
|
|
* FIXME I don't have the bar size so just guess PAGE_SIZE is more
|
|
* than enough. 1K is the biggest I have seen.
|
|
*/
|
|
set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
|
|
ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
|
|
ehci_bar += bar_val & ~PAGE_MASK;
|
|
dbgp_printk("ehci_bar: %p\n", ehci_bar);
|
|
|
|
ehci_caps = ehci_bar;
|
|
ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
|
|
ehci_debug = ehci_bar + offset;
|
|
ehci_dev.bus = bus;
|
|
ehci_dev.slot = slot;
|
|
ehci_dev.func = func;
|
|
|
|
detect_set_debug_port();
|
|
|
|
ret = ehci_setup();
|
|
if (ret < 0) {
|
|
dbgp_printk("ehci_setup failed\n");
|
|
ehci_debug = NULL;
|
|
|
|
return -1;
|
|
}
|
|
dbgp_ehci_status("early_init_complete");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void early_dbgp_write(struct console *con, const char *str, u32 n)
|
|
{
|
|
int chunk, ret;
|
|
char buf[DBGP_MAX_PACKET];
|
|
int use_cr = 0;
|
|
u32 cmd, ctrl;
|
|
int reset_run = 0;
|
|
|
|
if (!ehci_debug || dbgp_not_safe)
|
|
return;
|
|
|
|
cmd = readl(&ehci_regs->command);
|
|
if (unlikely(!(cmd & CMD_RUN))) {
|
|
/* If the ehci controller is not in the run state do extended
|
|
* checks to see if the acpi or some other initialization also
|
|
* reset the ehci debug port */
|
|
ctrl = readl(&ehci_debug->control);
|
|
if (!(ctrl & DBGP_ENABLED)) {
|
|
dbgp_not_safe = 1;
|
|
dbgp_external_startup();
|
|
} else {
|
|
cmd |= CMD_RUN;
|
|
writel(cmd, &ehci_regs->command);
|
|
reset_run = 1;
|
|
}
|
|
}
|
|
while (n > 0) {
|
|
for (chunk = 0; chunk < DBGP_MAX_PACKET && n > 0;
|
|
str++, chunk++, n--) {
|
|
if (!use_cr && *str == '\n') {
|
|
use_cr = 1;
|
|
buf[chunk] = '\r';
|
|
str--;
|
|
n++;
|
|
continue;
|
|
}
|
|
if (use_cr)
|
|
use_cr = 0;
|
|
buf[chunk] = *str;
|
|
}
|
|
if (chunk > 0) {
|
|
ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
|
|
dbgp_endpoint_out, buf, chunk);
|
|
}
|
|
}
|
|
if (unlikely(reset_run)) {
|
|
cmd = readl(&ehci_regs->command);
|
|
cmd &= ~CMD_RUN;
|
|
writel(cmd, &ehci_regs->command);
|
|
}
|
|
}
|
|
|
|
struct console early_dbgp_console = {
|
|
.name = "earlydbg",
|
|
.write = early_dbgp_write,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
};
|
|
|
|
int dbgp_reset_prep(void)
|
|
{
|
|
u32 ctrl;
|
|
|
|
dbgp_not_safe = 1;
|
|
if (!ehci_debug)
|
|
return 0;
|
|
|
|
if (early_dbgp_console.index != -1 &&
|
|
!(early_dbgp_console.flags & CON_BOOT))
|
|
return 1;
|
|
/* This means the console is not initialized, or should get
|
|
* shutdown so as to allow for reuse of the usb device, which
|
|
* means it is time to shutdown the usb debug port. */
|
|
ctrl = readl(&ehci_debug->control);
|
|
if (ctrl & DBGP_ENABLED) {
|
|
ctrl &= ~(DBGP_CLAIM);
|
|
writel(ctrl, &ehci_debug->control);
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dbgp_reset_prep);
|