73ce9aec65
IMC_MAX_PMU is used for static storage (per_nest_pmu_arr) which holds
nest pmu information. Current value for the macro is 32 based on
the initial number of nest pmu units supported by the nest microcode.
But going forward, microcode could support more nest units. Instead
of static storage, patch to fix the code to dynamically allocate an
array based on the number of nest imc units found in the device tree.
Fixes:8f95faaac56c1 ('powerpc/powernv: Detect and create IMC device')
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
#ifndef __ASM_POWERPC_IMC_PMU_H
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#define __ASM_POWERPC_IMC_PMU_H
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/*
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* IMC Nest Performance Monitor counter support.
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*
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* Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
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* (C) 2017 Anju T Sudhakar, IBM Corporation.
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* (C) 2017 Hemant K Shaw, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or later version.
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*/
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <asm/opal.h>
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/*
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* Compatibility macros for IMC devices
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*/
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#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
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#define IMC_DTB_UNIT_COMPAT "ibm,imc-counters"
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/*
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* LDBAR: Counter address and Enable/Disable macro.
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* perf/imc-pmu.c has the LDBAR layout information.
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*/
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#define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL
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#define THREAD_IMC_ENABLE 0x8000000000000000ULL
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/*
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* Structure to hold memory address information for imc units.
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*/
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struct imc_mem_info {
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u64 *vbase;
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u32 id;
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};
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/*
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* Place holder for nest pmu events and values.
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*/
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struct imc_events {
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u32 value;
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char *name;
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char *unit;
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char *scale;
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};
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/* Event attribute array index */
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#define IMC_FORMAT_ATTR 0
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#define IMC_EVENT_ATTR 1
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#define IMC_CPUMASK_ATTR 2
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#define IMC_NULL_ATTR 3
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/* PMU Format attribute macros */
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#define IMC_EVENT_OFFSET_MASK 0xffffffffULL
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/*
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* Device tree parser code detects IMC pmu support and
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* registers new IMC pmus. This structure will hold the
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* pmu functions, events, counter memory information
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* and attrs for each imc pmu and will be referenced at
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* the time of pmu registration.
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*/
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struct imc_pmu {
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struct pmu pmu;
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struct imc_mem_info *mem_info;
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struct imc_events **events;
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/*
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* Attribute groups for the PMU. Slot 0 used for
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* format attribute, slot 1 used for cpusmask attribute,
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* slot 2 used for event attribute. Slot 3 keep as
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* NULL.
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*/
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const struct attribute_group *attr_groups[4];
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u32 counter_mem_size;
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int domain;
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/*
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* flag to notify whether the memory is mmaped
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* or allocated by kernel.
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*/
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bool imc_counter_mmaped;
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};
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/*
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* Structure to hold id, lock and reference count for the imc events which
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* are inited.
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*/
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struct imc_pmu_ref {
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struct mutex lock;
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unsigned int id;
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int refc;
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};
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/*
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* In-Memory Collection Counters type.
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* Data comes from Device tree.
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* Three device type are supported.
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*/
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enum {
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IMC_TYPE_THREAD = 0x1,
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IMC_TYPE_CORE = 0x4,
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IMC_TYPE_CHIP = 0x10,
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};
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/*
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* Domains for IMC PMUs
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*/
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#define IMC_DOMAIN_NEST 1
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#define IMC_DOMAIN_CORE 2
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#define IMC_DOMAIN_THREAD 3
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extern int init_imc_pmu(struct device_node *parent,
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struct imc_pmu *pmu_ptr, int pmu_id);
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extern void thread_imc_disable(void);
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extern int get_max_nest_dev(void);
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#endif /* __ASM_POWERPC_IMC_PMU_H */
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