151 lines
3.3 KiB
C
151 lines
3.3 KiB
C
/*
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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/*
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* Simulator Platform-specific hooks for SMP operation
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/hardirq.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/smtc_ipi.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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/* VPE/SMP Prototype implements platform interfaces directly */
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#if !defined(CONFIG_MIPS_MT_SMP)
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/*
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* Cause the specified action to be performed on a targeted "CPU"
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*/
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void core_send_ipi(int cpu, unsigned int action)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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void smtc_send_ipi(int, int, unsigned int);
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smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
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#endif /* CONFIG_MIPS_MT_SMTC */
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/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
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}
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/*
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* Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
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*/
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void __init prom_build_cpu_map(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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extern int mipsmt_build_cpu_map(int startslot);
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int nextslot;
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cpus_clear(phys_cpu_present_map);
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/* Register the boot CPU */
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smp_prepare_boot_cpu();
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/*
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* As of November, 2004, MIPSsim only simulates one core
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* at a time. However, that core may be a MIPS MT core
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* with multiple virtual processors and thread contexts.
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*/
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if (read_c0_config3() & (1<<2)) {
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nextslot = mipsmt_build_cpu_map(1);
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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* Platform "CPU" startup hook
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*/
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void prom_boot_secondary(int cpu, struct task_struct *idle)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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extern void smtc_boot_secondary(int cpu, struct task_struct *t);
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smtc_boot_secondary(cpu, idle);
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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* Post-config but pre-boot cleanup entry point
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*/
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void prom_init_secondary(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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void smtc_init_secondary(void);
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smtc_init_secondary();
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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* Platform SMP pre-initialization
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*/
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void prom_prepare_cpus(unsigned int max_cpus)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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void mipsmt_prepare_cpus(int c);
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/*
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* As noted above, we can assume a single CPU for now
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* but it may be multithreaded.
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*/
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if (read_c0_config3() & (1<<2)) {
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mipsmt_prepare_cpus(max_cpus);
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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* SMP initialization finalization entry point
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*/
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void prom_smp_finish(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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void smtc_smp_finish(void);
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smtc_smp_finish();
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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/*
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* Hook for after all CPUs are online
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*/
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void prom_cpus_done(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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#endif /* CONFIG_MIPS32R2_MT_SMP */
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