51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
173 lines
5.6 KiB
C
173 lines
5.6 KiB
C
#ifndef __rt_trace_defs_h
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#define __rt_trace_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/rt_trace/rtl/rt_regs.r
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* id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
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* last modfied: Mon Apr 11 16:09:14 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
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* id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope rt_trace */
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/* Register rw_cfg, scope rt_trace, type rw */
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typedef struct {
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unsigned int en : 1;
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unsigned int mode : 1;
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unsigned int owner : 1;
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unsigned int wp : 1;
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unsigned int stall : 1;
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unsigned int dummy1 : 3;
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unsigned int wp_start : 7;
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unsigned int dummy2 : 1;
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unsigned int wp_stop : 7;
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unsigned int dummy3 : 9;
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} reg_rt_trace_rw_cfg;
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#define REG_RD_ADDR_rt_trace_rw_cfg 0
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#define REG_WR_ADDR_rt_trace_rw_cfg 0
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/* Register rw_tap_ctrl, scope rt_trace, type rw */
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typedef struct {
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unsigned int ack_data : 1;
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unsigned int ack_guru : 1;
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unsigned int dummy1 : 30;
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} reg_rt_trace_rw_tap_ctrl;
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#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
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#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
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/* Register r_tap_stat, scope rt_trace, type r */
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typedef struct {
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unsigned int dav : 1;
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unsigned int empty : 1;
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unsigned int dummy1 : 30;
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} reg_rt_trace_r_tap_stat;
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#define REG_RD_ADDR_rt_trace_r_tap_stat 8
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/* Register rw_tap_data, scope rt_trace, type rw */
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typedef unsigned int reg_rt_trace_rw_tap_data;
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#define REG_RD_ADDR_rt_trace_rw_tap_data 12
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#define REG_WR_ADDR_rt_trace_rw_tap_data 12
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/* Register rw_tap_hdata, scope rt_trace, type rw */
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typedef struct {
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unsigned int op : 4;
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unsigned int sub_op : 4;
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unsigned int dummy1 : 24;
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} reg_rt_trace_rw_tap_hdata;
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#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
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#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
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/* Register r_redir, scope rt_trace, type r */
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typedef unsigned int reg_rt_trace_r_redir;
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#define REG_RD_ADDR_rt_trace_r_redir 20
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/* Constants */
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enum {
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regk_rt_trace_brk = 0x0000000c,
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regk_rt_trace_dbg = 0x00000003,
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regk_rt_trace_dbgdi = 0x00000004,
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regk_rt_trace_dbgdo = 0x00000005,
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regk_rt_trace_gmode = 0x00000000,
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regk_rt_trace_no = 0x00000000,
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regk_rt_trace_nop = 0x00000000,
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regk_rt_trace_normal = 0x00000000,
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regk_rt_trace_rdmem = 0x00000007,
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regk_rt_trace_rdmemb = 0x00000009,
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regk_rt_trace_rdpreg = 0x00000002,
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regk_rt_trace_rdreg = 0x00000001,
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regk_rt_trace_rdsreg = 0x00000003,
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regk_rt_trace_redir = 0x00000006,
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regk_rt_trace_ret = 0x0000000b,
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regk_rt_trace_rw_cfg_default = 0x00000000,
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regk_rt_trace_trcfg = 0x00000001,
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regk_rt_trace_wp = 0x00000001,
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regk_rt_trace_wp0 = 0x00000001,
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regk_rt_trace_wp1 = 0x00000002,
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regk_rt_trace_wp2 = 0x00000004,
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regk_rt_trace_wp3 = 0x00000008,
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regk_rt_trace_wp4 = 0x00000010,
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regk_rt_trace_wp5 = 0x00000020,
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regk_rt_trace_wp6 = 0x00000040,
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regk_rt_trace_wrmem = 0x00000008,
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regk_rt_trace_wrmemb = 0x0000000a,
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regk_rt_trace_wrpreg = 0x00000005,
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regk_rt_trace_wrreg = 0x00000004,
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regk_rt_trace_wrsreg = 0x00000006,
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regk_rt_trace_yes = 0x00000001
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};
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#endif /* __rt_trace_defs_h */
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