6c6dc56c1e
- A couple of fields have changed name: reg_eth_rw_ga_lo.table -> tbl reg_eth_rw_ga_hi.table -> tbl reg_eth_rw_gen_ctrl.flow_ctrl_dis -> flow_ctrl - Add some new register fields. reg_eth_rw_gen_ctrl.gtxclk_out reg_eth_rw_gen_ctrl.phyrst_n reg_eth_rw_tr_ctrl.carrier_ext - max_size in reg_eth_rw_rec_ctrl had the wrong size. - Registers reg_eth_rw_mgm_ctrl and reg_eth_r_stat was reworked completely.
378 lines
11 KiB
C
378 lines
11 KiB
C
#ifndef __eth_defs_h
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#define __eth_defs_h
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/*
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* This file is autogenerated from
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* file: eth.r
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* id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
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* last modfied: Mon Jan 9 06:06:41 2006
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*
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* by /n/asic/design/tools/rdesc/rdes2c eth.r
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* id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope eth */
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/* Register rw_ma0_lo, scope eth, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_eth_rw_ma0_lo;
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#define REG_RD_ADDR_eth_rw_ma0_lo 0
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#define REG_WR_ADDR_eth_rw_ma0_lo 0
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/* Register rw_ma0_hi, scope eth, type rw */
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typedef struct {
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unsigned int addr : 16;
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unsigned int dummy1 : 16;
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} reg_eth_rw_ma0_hi;
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#define REG_RD_ADDR_eth_rw_ma0_hi 4
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#define REG_WR_ADDR_eth_rw_ma0_hi 4
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/* Register rw_ma1_lo, scope eth, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_eth_rw_ma1_lo;
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#define REG_RD_ADDR_eth_rw_ma1_lo 8
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#define REG_WR_ADDR_eth_rw_ma1_lo 8
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/* Register rw_ma1_hi, scope eth, type rw */
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typedef struct {
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unsigned int addr : 16;
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unsigned int dummy1 : 16;
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} reg_eth_rw_ma1_hi;
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#define REG_RD_ADDR_eth_rw_ma1_hi 12
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#define REG_WR_ADDR_eth_rw_ma1_hi 12
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/* Register rw_ga_lo, scope eth, type rw */
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typedef struct {
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unsigned int tbl : 32;
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} reg_eth_rw_ga_lo;
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#define REG_RD_ADDR_eth_rw_ga_lo 16
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#define REG_WR_ADDR_eth_rw_ga_lo 16
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/* Register rw_ga_hi, scope eth, type rw */
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typedef struct {
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unsigned int tbl : 32;
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} reg_eth_rw_ga_hi;
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#define REG_RD_ADDR_eth_rw_ga_hi 20
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#define REG_WR_ADDR_eth_rw_ga_hi 20
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/* Register rw_gen_ctrl, scope eth, type rw */
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typedef struct {
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unsigned int en : 1;
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unsigned int phy : 2;
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unsigned int protocol : 1;
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unsigned int loopback : 1;
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unsigned int flow_ctrl : 1;
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unsigned int gtxclk_out : 1;
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unsigned int phyrst_n : 1;
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unsigned int dummy1 : 24;
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} reg_eth_rw_gen_ctrl;
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#define REG_RD_ADDR_eth_rw_gen_ctrl 24
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#define REG_WR_ADDR_eth_rw_gen_ctrl 24
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/* Register rw_rec_ctrl, scope eth, type rw */
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typedef struct {
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unsigned int ma0 : 1;
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unsigned int ma1 : 1;
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unsigned int individual : 1;
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unsigned int broadcast : 1;
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unsigned int undersize : 1;
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unsigned int oversize : 1;
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unsigned int bad_crc : 1;
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unsigned int duplex : 1;
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unsigned int max_size : 16;
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unsigned int dummy1 : 8;
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} reg_eth_rw_rec_ctrl;
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#define REG_RD_ADDR_eth_rw_rec_ctrl 28
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#define REG_WR_ADDR_eth_rw_rec_ctrl 28
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/* Register rw_tr_ctrl, scope eth, type rw */
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typedef struct {
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unsigned int crc : 1;
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unsigned int pad : 1;
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unsigned int retry : 1;
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unsigned int ignore_col : 1;
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unsigned int cancel : 1;
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unsigned int hsh_delay : 1;
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unsigned int ignore_crs : 1;
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unsigned int carrier_ext : 1;
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unsigned int dummy1 : 24;
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} reg_eth_rw_tr_ctrl;
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#define REG_RD_ADDR_eth_rw_tr_ctrl 32
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#define REG_WR_ADDR_eth_rw_tr_ctrl 32
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/* Register rw_clr_err, scope eth, type rw */
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typedef struct {
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unsigned int clr : 1;
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unsigned int dummy1 : 31;
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} reg_eth_rw_clr_err;
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#define REG_RD_ADDR_eth_rw_clr_err 36
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#define REG_WR_ADDR_eth_rw_clr_err 36
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/* Register rw_mgm_ctrl, scope eth, type rw */
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typedef struct {
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unsigned int mdio : 1;
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unsigned int mdoe : 1;
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unsigned int mdc : 1;
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unsigned int dummy1 : 29;
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} reg_eth_rw_mgm_ctrl;
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#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
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#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
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/* Register r_stat, scope eth, type r */
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typedef struct {
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unsigned int mdio : 1;
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unsigned int exc_col : 1;
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unsigned int urun : 1;
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unsigned int clk_125 : 1;
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unsigned int dummy1 : 28;
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} reg_eth_r_stat;
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#define REG_RD_ADDR_eth_r_stat 44
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/* Register rs_rec_cnt, scope eth, type rs */
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typedef struct {
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unsigned int crc_err : 8;
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unsigned int align_err : 8;
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unsigned int oversize : 8;
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unsigned int congestion : 8;
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} reg_eth_rs_rec_cnt;
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#define REG_RD_ADDR_eth_rs_rec_cnt 48
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/* Register r_rec_cnt, scope eth, type r */
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typedef struct {
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unsigned int crc_err : 8;
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unsigned int align_err : 8;
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unsigned int oversize : 8;
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unsigned int congestion : 8;
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} reg_eth_r_rec_cnt;
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#define REG_RD_ADDR_eth_r_rec_cnt 52
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/* Register rs_tr_cnt, scope eth, type rs */
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typedef struct {
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unsigned int single_col : 8;
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unsigned int mult_col : 8;
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unsigned int late_col : 8;
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unsigned int deferred : 8;
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} reg_eth_rs_tr_cnt;
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#define REG_RD_ADDR_eth_rs_tr_cnt 56
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/* Register r_tr_cnt, scope eth, type r */
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typedef struct {
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unsigned int single_col : 8;
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unsigned int mult_col : 8;
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unsigned int late_col : 8;
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unsigned int deferred : 8;
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} reg_eth_r_tr_cnt;
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#define REG_RD_ADDR_eth_r_tr_cnt 60
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/* Register rs_phy_cnt, scope eth, type rs */
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typedef struct {
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unsigned int carrier_loss : 8;
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unsigned int sqe_err : 8;
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unsigned int dummy1 : 16;
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} reg_eth_rs_phy_cnt;
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#define REG_RD_ADDR_eth_rs_phy_cnt 64
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/* Register r_phy_cnt, scope eth, type r */
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typedef struct {
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unsigned int carrier_loss : 8;
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unsigned int sqe_err : 8;
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unsigned int dummy1 : 16;
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} reg_eth_r_phy_cnt;
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#define REG_RD_ADDR_eth_r_phy_cnt 68
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/* Register rw_test_ctrl, scope eth, type rw */
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typedef struct {
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unsigned int snmp_inc : 1;
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unsigned int snmp : 1;
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unsigned int backoff : 1;
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unsigned int dummy1 : 29;
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} reg_eth_rw_test_ctrl;
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#define REG_RD_ADDR_eth_rw_test_ctrl 72
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#define REG_WR_ADDR_eth_rw_test_ctrl 72
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/* Register rw_intr_mask, scope eth, type rw */
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typedef struct {
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unsigned int crc : 1;
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unsigned int align : 1;
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unsigned int oversize : 1;
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unsigned int congestion : 1;
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unsigned int single_col : 1;
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unsigned int mult_col : 1;
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unsigned int late_col : 1;
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unsigned int deferred : 1;
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unsigned int carrier_loss : 1;
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unsigned int sqe_test_err : 1;
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unsigned int orun : 1;
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unsigned int urun : 1;
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unsigned int exc_col : 1;
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unsigned int mdio : 1;
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unsigned int dummy1 : 18;
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} reg_eth_rw_intr_mask;
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#define REG_RD_ADDR_eth_rw_intr_mask 76
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#define REG_WR_ADDR_eth_rw_intr_mask 76
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/* Register rw_ack_intr, scope eth, type rw */
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typedef struct {
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unsigned int crc : 1;
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unsigned int align : 1;
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unsigned int oversize : 1;
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unsigned int congestion : 1;
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unsigned int single_col : 1;
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unsigned int mult_col : 1;
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unsigned int late_col : 1;
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unsigned int deferred : 1;
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unsigned int carrier_loss : 1;
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unsigned int sqe_test_err : 1;
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unsigned int orun : 1;
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unsigned int urun : 1;
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unsigned int exc_col : 1;
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unsigned int mdio : 1;
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unsigned int dummy1 : 18;
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} reg_eth_rw_ack_intr;
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#define REG_RD_ADDR_eth_rw_ack_intr 80
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#define REG_WR_ADDR_eth_rw_ack_intr 80
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/* Register r_intr, scope eth, type r */
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typedef struct {
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unsigned int crc : 1;
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unsigned int align : 1;
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unsigned int oversize : 1;
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unsigned int congestion : 1;
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unsigned int single_col : 1;
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unsigned int mult_col : 1;
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unsigned int late_col : 1;
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unsigned int deferred : 1;
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unsigned int carrier_loss : 1;
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unsigned int sqe_test_err : 1;
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unsigned int orun : 1;
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unsigned int urun : 1;
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unsigned int exc_col : 1;
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unsigned int mdio : 1;
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unsigned int dummy1 : 18;
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} reg_eth_r_intr;
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#define REG_RD_ADDR_eth_r_intr 84
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/* Register r_masked_intr, scope eth, type r */
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typedef struct {
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unsigned int crc : 1;
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unsigned int align : 1;
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unsigned int oversize : 1;
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unsigned int congestion : 1;
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unsigned int single_col : 1;
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unsigned int mult_col : 1;
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unsigned int late_col : 1;
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unsigned int deferred : 1;
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unsigned int carrier_loss : 1;
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unsigned int sqe_test_err : 1;
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unsigned int orun : 1;
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unsigned int urun : 1;
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unsigned int exc_col : 1;
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unsigned int mdio : 1;
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unsigned int dummy1 : 18;
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} reg_eth_r_masked_intr;
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#define REG_RD_ADDR_eth_r_masked_intr 88
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/* Constants */
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enum {
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regk_eth_discard = 0x00000000,
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regk_eth_ether = 0x00000000,
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regk_eth_full = 0x00000001,
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regk_eth_gmii = 0x00000003,
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regk_eth_gtxclk = 0x00000001,
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regk_eth_half = 0x00000000,
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regk_eth_hsh = 0x00000001,
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regk_eth_mii = 0x00000001,
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regk_eth_mii_arec = 0x00000002,
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regk_eth_mii_clk = 0x00000000,
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regk_eth_no = 0x00000000,
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regk_eth_phyrst = 0x00000000,
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regk_eth_rec = 0x00000001,
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regk_eth_rw_ga_hi_default = 0x00000000,
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regk_eth_rw_ga_lo_default = 0x00000000,
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regk_eth_rw_gen_ctrl_default = 0x00000000,
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regk_eth_rw_intr_mask_default = 0x00000000,
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regk_eth_rw_ma0_hi_default = 0x00000000,
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regk_eth_rw_ma0_lo_default = 0x00000000,
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regk_eth_rw_ma1_hi_default = 0x00000000,
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regk_eth_rw_ma1_lo_default = 0x00000000,
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regk_eth_rw_mgm_ctrl_default = 0x00000000,
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regk_eth_rw_test_ctrl_default = 0x00000000,
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regk_eth_size1518 = 0x000005ee,
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regk_eth_size1522 = 0x000005f2,
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regk_eth_yes = 0x00000001
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};
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#endif /* __eth_defs_h */
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