4de563ae82
This patch adds an irqchip driver for the main interrupt controller found on MOXA ART SoCs. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Cc: grant.likely@secretlab.ca Cc: thomas.petazzoni@free-electrons.com Cc: arnd@arndb.de Cc: u.kleine-koenig@pengutronix.de Cc: linux@arm.linux.org.uk Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1372941531-6393-1-git-send-email-jonas.jensen@gmail.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/*
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* MOXA ART SoCs IRQ chip driver.
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*
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* Copyright (C) 2013 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define IRQ_SOURCE_REG 0
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#define IRQ_MASK_REG 0x04
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#define IRQ_CLEAR_REG 0x08
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#define IRQ_MODE_REG 0x0c
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#define IRQ_LEVEL_REG 0x10
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#define IRQ_STATUS_REG 0x14
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#define FIQ_SOURCE_REG 0x20
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#define FIQ_MASK_REG 0x24
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#define FIQ_CLEAR_REG 0x28
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#define FIQ_MODE_REG 0x2c
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#define FIQ_LEVEL_REG 0x30
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#define FIQ_STATUS_REG 0x34
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struct moxart_irq_data {
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void __iomem *base;
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struct irq_domain *domain;
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unsigned int interrupt_mask;
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};
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static struct moxart_irq_data intc;
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static asmlinkage void __exception_irq_entry handle_irq(struct pt_regs *regs)
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{
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u32 irqstat;
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int hwirq;
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irqstat = readl(intc.base + IRQ_STATUS_REG);
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while (irqstat) {
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hwirq = ffs(irqstat) - 1;
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handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
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irqstat &= ~(1 << hwirq);
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}
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}
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static int __init moxart_of_intc_init(struct device_node *node,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int ret;
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struct irq_chip_generic *gc;
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intc.base = of_iomap(node, 0);
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if (!intc.base) {
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pr_err("%s: unable to map IC registers\n",
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node->full_name);
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return -EINVAL;
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}
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intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
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intc.base);
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if (!intc.domain) {
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pr_err("%s: unable to create IRQ domain\n", node->full_name);
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return -EINVAL;
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}
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ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1,
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"MOXARTINTC", handle_edge_irq,
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clr, 0, IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%s: could not allocate generic chip\n",
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node->full_name);
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irq_domain_remove(intc.domain);
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return -EINVAL;
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}
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ret = of_property_read_u32(node, "interrupt-mask",
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&intc.interrupt_mask);
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if (ret)
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pr_err("%s: could not read interrupt-mask DT property\n",
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node->full_name);
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gc = irq_get_domain_generic_chip(intc.domain, 0);
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gc->reg_base = intc.base;
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gc->chip_types[0].regs.mask = IRQ_MASK_REG;
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gc->chip_types[0].regs.ack = IRQ_CLEAR_REG;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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writel(0, intc.base + IRQ_MASK_REG);
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writel(0xffffffff, intc.base + IRQ_CLEAR_REG);
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writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG);
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writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG);
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set_handle_irq(handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-ic", moxart_of_intc_init);
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