f12d0d7c77
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:
Related operation Safe condition
a. any CP15 access !CPU_CP15
b. alignment trap CPU_CP15_MMU
c. D-cache(C-bit) CPU_CP15
d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
CPU_ARM720 || CPU_ARM740 ||
CPU_XSCALE || CPU_XSC3 )
e. alternate vector CPU_CP15 && !CPU_ARM740
f. TTB CPU_CP15_MMU
g. Domain CPU_CP15_MMU
h. FSR/FAR CPU_CP15_MMU
For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
52 lines
1.5 KiB
Text
52 lines
1.5 KiB
Text
#
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# Kconfig for uClinux(non-paged MM) depend configurations
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# Hyok S. Choi <hyok.choi@samsung.com>
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#
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config SET_MEM_PARAM
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bool "Set flash/sdram size and base addr"
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help
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Say Y to manually set the base addresses and sizes.
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otherwise, the default values are assigned.
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config DRAM_BASE
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hex '(S)DRAM Base Address' if SET_MEM_PARAM
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default 0x00800000
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config DRAM_SIZE
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hex '(S)DRAM SIZE' if SET_MEM_PARAM
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default 0x00800000
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config FLASH_MEM_BASE
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hex 'FLASH Base Address' if SET_MEM_PARAM
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default 0x00400000
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config FLASH_SIZE
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hex 'FLASH Size' if SET_MEM_PARAM
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default 0x00400000
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config PROCESSOR_ID
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hex
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default 0x00007700
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depends on !CPU_CP15
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help
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If processor has no CP15 register, this processor ID is
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used instead of the auto-probing which utilizes the register.
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config REMAP_VECTORS_TO_RAM
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bool 'Install vectors to the begining of RAM' if DRAM_BASE
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depends on DRAM_BASE
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help
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The kernel needs to change the hardware exception vectors.
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In nommu mode, the hardware exception vectors are normally
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placed at address 0x00000000. However, this region may be
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occupied by read-only memory depending on H/W design.
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If the region contains read-write memory, say 'n' here.
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If your CPU provides a remap facility which allows the exception
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vectors to be mapped to writable memory, say 'n' here.
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Otherwise, say 'y' here. In this case, the kernel will require
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external support to redirect the hardware exception vectors to
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the writable versions located at DRAM_BASE.
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