4b402e3a54
The traps test case 21 "exception 0x3f: l1_instruction_access" would make the kernel panic on BF533's because we end up calling show_stack() infinitely. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
201 lines
5.7 KiB
C
201 lines
5.7 KiB
C
/*
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* Description: Instruction SRAM accessor functions for the Blackfin
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*
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* Copyright 2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <asm/blackfin.h>
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/*
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* IMPORTANT WARNING ABOUT THESE FUNCTIONS
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*
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* The emulator will not function correctly if a write command is left in
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* ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
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* the emulator. To avoid such problems, ensure that both ITEST_COMMAND
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* and DTEST_COMMAND are zero when exiting these functions.
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*/
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/*
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* On the Blackfin, L1 instruction sram (which operates at core speeds) can not
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* be accessed by a normal core load, so we need to go through a few hoops to
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* read/write it.
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* To try to make it easier - we export a memcpy interface, where either src or
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* dest can be in this special L1 memory area.
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* The low level read/write functions should not be exposed to the rest of the
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* kernel, since they operate on 64-bit data, and need specific address alignment
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*/
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static DEFINE_SPINLOCK(dtest_lock);
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/* Takes a void pointer */
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#define IADDR2DTEST(x) \
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({ unsigned long __addr = (unsigned long)(x); \
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(__addr & 0x47F8) | /* address bits 14 & 10:3 */ \
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(__addr & 0x0800) << 15 | /* address bit 11 */ \
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(__addr & 0x3000) << 4 | /* address bits 13:12 */ \
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(__addr & 0x8000) << 8 | /* address bit 15 */ \
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(0x1000004); /* isram access */ \
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})
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/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
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#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
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/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
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#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
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static void isram_write(const void *addr, uint64_t data)
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{
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uint32_t cmd;
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unsigned long flags;
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if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
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return;
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cmd = IADDR2DTEST(addr) | 1; /* write */
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/*
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* Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
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* While in exception context - atomicity is guaranteed or double fault
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*/
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spin_lock_irqsave(&dtest_lock, flags);
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bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
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bfin_write_DTEST_DATA1(data >> 32);
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/* use the builtin, since interrupts are already turned off */
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(cmd);
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(0);
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__builtin_bfin_csync();
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spin_unlock_irqrestore(&dtest_lock, flags);
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}
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static uint64_t isram_read(const void *addr)
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{
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uint32_t cmd;
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unsigned long flags;
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uint64_t ret;
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if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
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return 0;
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cmd = IADDR2DTEST(addr) | 0; /* read */
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/*
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* Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
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* While in exception context - atomicity is guaranteed or double fault
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*/
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spin_lock_irqsave(&dtest_lock, flags);
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/* use the builtin, since interrupts are already turned off */
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__builtin_bfin_csync();
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bfin_write_DTEST_COMMAND(cmd);
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__builtin_bfin_csync();
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ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
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bfin_write_DTEST_COMMAND(0);
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__builtin_bfin_csync();
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spin_unlock_irqrestore(&dtest_lock, flags);
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return ret;
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}
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static bool isram_check_addr(const void *addr, size_t n)
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{
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if ((addr >= (void *)L1_CODE_START) &&
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(addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
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if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
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show_stack(NULL, NULL);
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printk(KERN_ERR "isram_memcpy: copy involving %p length "
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"(%zu) too long\n", addr, n);
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}
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return true;
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}
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return false;
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}
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/*
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* The isram_memcpy() function copies n bytes from memory area src to memory area dest.
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* The isram_memcpy() function returns a pointer to dest.
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* Either dest or src can be in L1 instruction sram.
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*/
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void *isram_memcpy(void *dest, const void *src, size_t n)
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{
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uint64_t data_in = 0, data_out = 0;
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size_t count;
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bool dest_in_l1, src_in_l1, need_data, put_data;
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unsigned char byte, *src_byte, *dest_byte;
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src_byte = (unsigned char *)src;
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dest_byte = (unsigned char *)dest;
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dest_in_l1 = isram_check_addr(dest, n);
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src_in_l1 = isram_check_addr(src, n);
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need_data = true;
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put_data = true;
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for (count = 0; count < n; count++) {
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if (src_in_l1) {
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if (need_data) {
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data_in = isram_read(src + count);
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need_data = false;
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}
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if (ADDR2LAST(src + count))
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need_data = true;
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byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
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} else {
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/* src is in L2 or L3 - so just dereference*/
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byte = src_byte[count];
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}
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if (dest_in_l1) {
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if (put_data) {
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data_out = isram_read(dest + count);
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put_data = false;
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}
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data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
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data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
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if (ADDR2LAST(dest + count)) {
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put_data = true;
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isram_write(dest + count, data_out);
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}
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} else {
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/* dest in L2 or L3 - so just dereference */
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dest_byte[count] = byte;
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}
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}
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/* make sure we dump the last byte if necessary */
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if (dest_in_l1 && !put_data)
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isram_write(dest + count, data_out);
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return dest;
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}
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EXPORT_SYMBOL(isram_memcpy);
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