8880f4ec21
This integrates support for the SFC9000 family of 10G Ethernet controllers and LAN-on-motherboard chips, starting with the SFL9021 'Siena' and SFC9020 'Bethpage'. Credit for this code is largely due to my colleagues at Solarflare: Guido Barzini Steve Hodgson Kieran Mansley Matthew Slattery Neil Turton Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2007-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_PHY_H
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#define EFX_PHY_H
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/****************************************************************************
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* 10Xpress (SFX7101 and SFT9001) PHYs
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*/
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extern struct efx_phy_operations falcon_sfx7101_phy_ops;
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extern struct efx_phy_operations falcon_sft9001_phy_ops;
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extern void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode);
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/* Wait for the PHY to boot. Return 0 on success, -EINVAL if the PHY failed
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* to boot due to corrupt flash, or some other negative error code. */
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extern int sft9001_wait_boot(struct efx_nic *efx);
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/****************************************************************************
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* AMCC/Quake QT202x PHYs
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*/
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extern struct efx_phy_operations falcon_qt202x_phy_ops;
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/* These PHYs provide various H/W control states for LEDs */
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#define QUAKE_LED_LINK_INVAL (0)
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#define QUAKE_LED_LINK_STAT (1)
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#define QUAKE_LED_LINK_ACT (2)
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#define QUAKE_LED_LINK_ACTSTAT (3)
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#define QUAKE_LED_OFF (4)
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#define QUAKE_LED_ON (5)
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#define QUAKE_LED_LINK_INPUT (6) /* Pin is an input. */
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/* What link the LED tracks */
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#define QUAKE_LED_TXLINK (0)
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#define QUAKE_LED_RXLINK (8)
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extern void falcon_qt202x_set_led(struct efx_nic *p, int led, int state);
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/****************************************************************************
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* Siena managed PHYs
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*/
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extern struct efx_phy_operations efx_mcdi_phy_ops;
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extern int efx_mcdi_mdio_read(struct efx_nic *efx, unsigned int bus,
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unsigned int prtad, unsigned int devad,
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u16 addr, u16 *value_out, u32 *status_out);
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extern int efx_mcdi_mdio_write(struct efx_nic *efx, unsigned int bus,
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unsigned int prtad, unsigned int devad,
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u16 addr, u16 value, u32 *status_out);
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extern void efx_mcdi_phy_decode_link(struct efx_nic *efx,
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struct efx_link_state *link_state,
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u32 speed, u32 flags, u32 fcntl);
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extern int efx_mcdi_phy_reconfigure(struct efx_nic *efx);
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extern void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa);
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#endif
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