87c441e54d
So far, MPC512x used mpc512x_find_ips_freq() to get the bus frequency, while MPC52xx used mpc52xx_find_ipb_freq(). Despite the different clock names (IPS vs. IPB) the code was identical. Use common code for both processor families. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
927 lines
26 KiB
C
927 lines
26 KiB
C
/*
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* drivers/ata/pata_mpc52xx.c
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*
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* libata driver for the Freescale MPC52xx on-chip IDE interface
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*
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* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
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*
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* UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
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* Domen Puncer and Tim Yamin.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/libata.h>
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#include <linux/of_platform.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/prom.h>
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#include <asm/mpc52xx.h>
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#include <sysdev/bestcomm/bestcomm.h>
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#include <sysdev/bestcomm/bestcomm_priv.h>
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#include <sysdev/bestcomm/ata.h>
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#define DRV_NAME "mpc52xx_ata"
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/* Private structures used by the driver */
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struct mpc52xx_ata_timings {
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u32 pio1;
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u32 pio2;
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u32 mdma1;
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u32 mdma2;
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u32 udma1;
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u32 udma2;
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u32 udma3;
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u32 udma4;
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u32 udma5;
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int using_udma;
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};
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struct mpc52xx_ata_priv {
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unsigned int ipb_period;
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struct mpc52xx_ata __iomem *ata_regs;
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phys_addr_t ata_regs_pa;
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int ata_irq;
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struct mpc52xx_ata_timings timings[2];
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int csel;
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/* DMA */
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struct bcom_task *dmatsk;
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const struct udmaspec *udmaspec;
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const struct mdmaspec *mdmaspec;
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int mpc52xx_ata_dma_last_write;
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int waiting_for_dma;
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};
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/* ATAPI-4 PIO specs (in ns) */
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static const int ataspec_t0[5] = {600, 383, 240, 180, 120};
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static const int ataspec_t1[5] = { 70, 50, 30, 30, 25};
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static const int ataspec_t2_8[5] = {290, 290, 290, 80, 70};
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static const int ataspec_t2_16[5] = {165, 125, 100, 80, 70};
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static const int ataspec_t2i[5] = { 0, 0, 0, 70, 25};
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static const int ataspec_t4[5] = { 30, 20, 15, 10, 10};
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static const int ataspec_ta[5] = { 35, 35, 35, 35, 35};
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#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
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/* ======================================================================== */
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/* ATAPI-4 MDMA specs (in clocks) */
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struct mdmaspec {
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u32 t0M;
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u32 td;
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u32 th;
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u32 tj;
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u32 tkw;
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u32 tm;
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u32 tn;
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};
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static const struct mdmaspec mdmaspec66[3] = {
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{ .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 },
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{ .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 },
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{ .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 },
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};
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static const struct mdmaspec mdmaspec132[3] = {
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{ .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 },
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{ .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 },
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{ .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 },
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};
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/* ATAPI-4 UDMA specs (in clocks) */
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struct udmaspec {
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u32 tcyc;
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u32 t2cyc;
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u32 tds;
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u32 tdh;
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u32 tdvs;
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u32 tdvh;
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u32 tfs;
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u32 tli;
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u32 tmli;
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u32 taz;
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u32 tzah;
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u32 tenv;
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u32 tsr;
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u32 trfs;
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u32 trp;
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u32 tack;
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u32 tss;
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};
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static const struct udmaspec udmaspec66[6] = {
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{ .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
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.tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4,
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},
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{ .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1,
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.tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4,
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},
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{ .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
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.tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
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},
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{ .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1,
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.tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
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},
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{ .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
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.tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
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},
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{ .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
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.tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4,
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},
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};
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static const struct udmaspec udmaspec132[6] = {
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{ .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1,
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.tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
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.tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7,
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},
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{ .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1,
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.tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
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.tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7,
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},
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{ .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
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.tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
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.tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
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},
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{ .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
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.tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
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.tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
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},
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{ .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1,
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.tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
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.tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6,
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},
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{ .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
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.tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
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.tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7,
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},
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};
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/* ======================================================================== */
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/* Bit definitions inside the registers */
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#define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
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#define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
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#define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
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#define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
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#define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
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#define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
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#define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
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#define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
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#define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
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#define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */
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#define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
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#define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
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#define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
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#define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
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#define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
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#define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
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#define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
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#define MAX_DMA_BUFFERS 128
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#define MAX_DMA_BUFFER_SIZE 0x20000u
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/* Structure of the hardware registers */
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struct mpc52xx_ata {
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/* Host interface registers */
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u32 config; /* ATA + 0x00 Host configuration */
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u32 host_status; /* ATA + 0x04 Host controller status */
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u32 pio1; /* ATA + 0x08 PIO Timing 1 */
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u32 pio2; /* ATA + 0x0c PIO Timing 2 */
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u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
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u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
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u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
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u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
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u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
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u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
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u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
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u32 share_cnt; /* ATA + 0x2c ATA share counter */
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u32 reserved0[3];
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/* FIFO registers */
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u32 fifo_data; /* ATA + 0x3c */
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u8 fifo_status_frame; /* ATA + 0x40 */
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u8 fifo_status; /* ATA + 0x41 */
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u16 reserved7[1];
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u8 fifo_control; /* ATA + 0x44 */
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u8 reserved8[5];
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u16 fifo_alarm; /* ATA + 0x4a */
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u16 reserved9;
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u16 fifo_rdp; /* ATA + 0x4e */
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u16 reserved10;
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u16 fifo_wrp; /* ATA + 0x52 */
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u16 reserved11;
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u16 fifo_lfrdp; /* ATA + 0x56 */
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u16 reserved12;
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u16 fifo_lfwrp; /* ATA + 0x5a */
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/* Drive TaskFile registers */
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u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
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u8 reserved13[3];
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u16 tf_data; /* ATA + 0x60 TASKFILE Data */
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u16 reserved14;
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u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
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u8 reserved15[3];
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u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
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u8 reserved16[3];
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u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
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u8 reserved17[3];
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u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
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u8 reserved18[3];
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u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
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u8 reserved19[3];
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u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
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u8 reserved20[3];
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u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
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u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
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u8 reserved21[2];
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};
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/* ======================================================================== */
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/* Aux fns */
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/* ======================================================================== */
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/* MPC52xx low level hw control */
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static int
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mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
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{
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struct mpc52xx_ata_timings *timing = &priv->timings[dev];
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unsigned int ipb_period = priv->ipb_period;
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unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
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if ((pio < 0) || (pio > 4))
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return -EINVAL;
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t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
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t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
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t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
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t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
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t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
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t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
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ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
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timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
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timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
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return 0;
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}
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static int
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mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
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int speed)
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{
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struct mpc52xx_ata_timings *t = &priv->timings[dev];
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const struct mdmaspec *s = &priv->mdmaspec[speed];
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if (speed < 0 || speed > 2)
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return -EINVAL;
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t->mdma1 = (s->t0M << 24) | (s->td << 16) | (s->tkw << 8) | (s->tm);
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t->mdma2 = (s->th << 24) | (s->tj << 16) | (s->tn << 8);
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t->using_udma = 0;
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return 0;
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}
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static int
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mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
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int speed)
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{
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struct mpc52xx_ata_timings *t = &priv->timings[dev];
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const struct udmaspec *s = &priv->udmaspec[speed];
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if (speed < 0 || speed > 2)
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return -EINVAL;
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t->udma1 = (s->t2cyc << 24) | (s->tcyc << 16) | (s->tds << 8) | s->tdh;
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t->udma2 = (s->tdvs << 24) | (s->tdvh << 16) | (s->tfs << 8) | s->tli;
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t->udma3 = (s->tmli << 24) | (s->taz << 16) | (s->tenv << 8) | s->tsr;
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t->udma4 = (s->tss << 24) | (s->trfs << 16) | (s->trp << 8) | s->tack;
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t->udma5 = (s->tzah << 24);
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t->using_udma = 1;
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return 0;
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}
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static void
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mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
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{
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struct mpc52xx_ata __iomem *regs = priv->ata_regs;
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struct mpc52xx_ata_timings *timing = &priv->timings[device];
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out_be32(®s->pio1, timing->pio1);
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out_be32(®s->pio2, timing->pio2);
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out_be32(®s->mdma1, timing->mdma1);
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out_be32(®s->mdma2, timing->mdma2);
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out_be32(®s->udma1, timing->udma1);
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out_be32(®s->udma2, timing->udma2);
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out_be32(®s->udma3, timing->udma3);
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out_be32(®s->udma4, timing->udma4);
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out_be32(®s->udma5, timing->udma5);
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priv->csel = device;
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}
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static int
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mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
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{
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struct mpc52xx_ata __iomem *regs = priv->ata_regs;
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int tslot;
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/* Clear share_cnt (all sample code do this ...) */
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out_be32(®s->share_cnt, 0);
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/* Configure and reset host */
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out_be32(®s->config,
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MPC52xx_ATA_HOSTCONF_IE |
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MPC52xx_ATA_HOSTCONF_IORDY |
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MPC52xx_ATA_HOSTCONF_SMR |
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MPC52xx_ATA_HOSTCONF_FR);
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udelay(10);
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out_be32(®s->config,
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MPC52xx_ATA_HOSTCONF_IE |
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MPC52xx_ATA_HOSTCONF_IORDY);
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/* Set the time slot to 1us */
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tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
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out_be32(®s->share_cnt, tslot << 16);
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/* Init timings to PIO0 */
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memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
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mpc52xx_ata_compute_pio_timings(priv, 0, 0);
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mpc52xx_ata_compute_pio_timings(priv, 1, 0);
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mpc52xx_ata_apply_timings(priv, 0);
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return 0;
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}
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/* ======================================================================== */
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/* libata driver */
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/* ======================================================================== */
|
|
|
|
static void
|
|
mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
|
|
{
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
int pio, rv;
|
|
|
|
pio = adev->pio_mode - XFER_PIO_0;
|
|
|
|
rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
|
|
|
|
if (rv) {
|
|
dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio);
|
|
return;
|
|
}
|
|
|
|
mpc52xx_ata_apply_timings(priv, adev->devno);
|
|
}
|
|
|
|
static void
|
|
mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
|
|
{
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
int rv;
|
|
|
|
if (adev->dma_mode >= XFER_UDMA_0) {
|
|
int dma = adev->dma_mode - XFER_UDMA_0;
|
|
rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma);
|
|
} else {
|
|
int dma = adev->dma_mode - XFER_MW_DMA_0;
|
|
rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma);
|
|
}
|
|
|
|
if (rv) {
|
|
dev_alert(ap->dev,
|
|
"Trying to select invalid DMA mode %d\n",
|
|
adev->dma_mode);
|
|
return;
|
|
}
|
|
|
|
mpc52xx_ata_apply_timings(priv, adev->devno);
|
|
}
|
|
|
|
static void
|
|
mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
|
|
{
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
|
|
if (device != priv->csel)
|
|
mpc52xx_ata_apply_timings(priv, device);
|
|
|
|
ata_sff_dev_select(ap, device);
|
|
}
|
|
|
|
static int
|
|
mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
struct bcom_ata_bd *bd;
|
|
unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si;
|
|
struct scatterlist *sg;
|
|
int count = 0;
|
|
|
|
if (read)
|
|
bcom_ata_rx_prepare(priv->dmatsk);
|
|
else
|
|
bcom_ata_tx_prepare(priv->dmatsk);
|
|
|
|
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
|
dma_addr_t cur_addr = sg_dma_address(sg);
|
|
u32 cur_len = sg_dma_len(sg);
|
|
|
|
while (cur_len) {
|
|
unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE);
|
|
bd = (struct bcom_ata_bd *)
|
|
bcom_prepare_next_buffer(priv->dmatsk);
|
|
|
|
if (read) {
|
|
bd->status = tc;
|
|
bd->src_pa = (__force u32) priv->ata_regs_pa +
|
|
offsetof(struct mpc52xx_ata, fifo_data);
|
|
bd->dst_pa = (__force u32) cur_addr;
|
|
} else {
|
|
bd->status = tc;
|
|
bd->src_pa = (__force u32) cur_addr;
|
|
bd->dst_pa = (__force u32) priv->ata_regs_pa +
|
|
offsetof(struct mpc52xx_ata, fifo_data);
|
|
}
|
|
|
|
bcom_submit_next_buffer(priv->dmatsk, NULL);
|
|
|
|
cur_addr += tc;
|
|
cur_len -= tc;
|
|
count++;
|
|
|
|
if (count > MAX_DMA_BUFFERS) {
|
|
dev_alert(ap->dev, "dma table"
|
|
"too small\n");
|
|
goto use_pio_instead;
|
|
}
|
|
}
|
|
}
|
|
return 1;
|
|
|
|
use_pio_instead:
|
|
bcom_ata_reset_bd(priv->dmatsk);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mpc52xx_bmdma_setup(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
struct mpc52xx_ata __iomem *regs = priv->ata_regs;
|
|
|
|
unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE);
|
|
u8 dma_mode;
|
|
|
|
if (!mpc52xx_ata_build_dmatable(qc))
|
|
dev_alert(ap->dev, "%s: %i, return 1?\n",
|
|
__func__, __LINE__);
|
|
|
|
/* Check FIFO is OK... */
|
|
if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
|
|
dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
|
|
__func__, in_8(&priv->ata_regs->fifo_status));
|
|
|
|
if (read) {
|
|
dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ |
|
|
MPC52xx_ATA_DMAMODE_FE;
|
|
|
|
/* Setup FIFO if direction changed */
|
|
if (priv->mpc52xx_ata_dma_last_write != 0) {
|
|
priv->mpc52xx_ata_dma_last_write = 0;
|
|
|
|
/* Configure FIFO with granularity to 7 */
|
|
out_8(®s->fifo_control, 7);
|
|
out_be16(®s->fifo_alarm, 128);
|
|
|
|
/* Set FIFO Reset bit (FR) */
|
|
out_8(®s->dma_mode, MPC52xx_ATA_DMAMODE_FR);
|
|
}
|
|
} else {
|
|
dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE;
|
|
|
|
/* Setup FIFO if direction changed */
|
|
if (priv->mpc52xx_ata_dma_last_write != 1) {
|
|
priv->mpc52xx_ata_dma_last_write = 1;
|
|
|
|
/* Configure FIFO with granularity to 4 */
|
|
out_8(®s->fifo_control, 4);
|
|
out_be16(®s->fifo_alarm, 128);
|
|
}
|
|
}
|
|
|
|
if (priv->timings[qc->dev->devno].using_udma)
|
|
dma_mode |= MPC52xx_ATA_DMAMODE_UDMA;
|
|
|
|
out_8(®s->dma_mode, dma_mode);
|
|
priv->waiting_for_dma = ATA_DMA_ACTIVE;
|
|
|
|
ata_wait_idle(ap);
|
|
ap->ops->sff_exec_command(ap, &qc->tf);
|
|
}
|
|
|
|
static void
|
|
mpc52xx_bmdma_start(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
|
|
bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum);
|
|
bcom_enable(priv->dmatsk);
|
|
}
|
|
|
|
static void
|
|
mpc52xx_bmdma_stop(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
|
|
bcom_disable(priv->dmatsk);
|
|
bcom_ata_reset_bd(priv->dmatsk);
|
|
priv->waiting_for_dma = 0;
|
|
|
|
/* Check FIFO is OK... */
|
|
if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
|
|
dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
|
|
__func__, in_8(&priv->ata_regs->fifo_status));
|
|
}
|
|
|
|
static u8
|
|
mpc52xx_bmdma_status(struct ata_port *ap)
|
|
{
|
|
struct mpc52xx_ata_priv *priv = ap->host->private_data;
|
|
|
|
/* Check FIFO is OK... */
|
|
if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) {
|
|
dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
|
|
__func__, in_8(&priv->ata_regs->fifo_status));
|
|
return priv->waiting_for_dma | ATA_DMA_ERR;
|
|
}
|
|
|
|
return priv->waiting_for_dma;
|
|
}
|
|
|
|
static irqreturn_t
|
|
mpc52xx_ata_task_irq(int irq, void *vpriv)
|
|
{
|
|
struct mpc52xx_ata_priv *priv = vpriv;
|
|
while (bcom_buffer_done(priv->dmatsk))
|
|
bcom_retrieve_buffer(priv->dmatsk, NULL, NULL);
|
|
|
|
priv->waiting_for_dma |= ATA_DMA_INTR;
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct scsi_host_template mpc52xx_ata_sht = {
|
|
ATA_PIO_SHT(DRV_NAME),
|
|
};
|
|
|
|
static struct ata_port_operations mpc52xx_ata_port_ops = {
|
|
.inherits = &ata_sff_port_ops,
|
|
.sff_dev_select = mpc52xx_ata_dev_select,
|
|
.set_piomode = mpc52xx_ata_set_piomode,
|
|
.set_dmamode = mpc52xx_ata_set_dmamode,
|
|
.bmdma_setup = mpc52xx_bmdma_setup,
|
|
.bmdma_start = mpc52xx_bmdma_start,
|
|
.bmdma_stop = mpc52xx_bmdma_stop,
|
|
.bmdma_status = mpc52xx_bmdma_status,
|
|
.qc_prep = ata_noop_qc_prep,
|
|
};
|
|
|
|
static int __devinit
|
|
mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv,
|
|
unsigned long raw_ata_regs, int mwdma_mask, int udma_mask)
|
|
{
|
|
struct ata_host *host;
|
|
struct ata_port *ap;
|
|
struct ata_ioports *aio;
|
|
|
|
host = ata_host_alloc(dev, 1);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
ap = host->ports[0];
|
|
ap->flags |= ATA_FLAG_SLAVE_POSS;
|
|
ap->pio_mask = ATA_PIO4;
|
|
ap->mwdma_mask = mwdma_mask;
|
|
ap->udma_mask = udma_mask;
|
|
ap->ops = &mpc52xx_ata_port_ops;
|
|
host->private_data = priv;
|
|
|
|
aio = &ap->ioaddr;
|
|
aio->cmd_addr = NULL; /* Don't have a classic reg block */
|
|
aio->altstatus_addr = &priv->ata_regs->tf_control;
|
|
aio->ctl_addr = &priv->ata_regs->tf_control;
|
|
aio->data_addr = &priv->ata_regs->tf_data;
|
|
aio->error_addr = &priv->ata_regs->tf_features;
|
|
aio->feature_addr = &priv->ata_regs->tf_features;
|
|
aio->nsect_addr = &priv->ata_regs->tf_sec_count;
|
|
aio->lbal_addr = &priv->ata_regs->tf_sec_num;
|
|
aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
|
|
aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
|
|
aio->device_addr = &priv->ata_regs->tf_dev_head;
|
|
aio->status_addr = &priv->ata_regs->tf_command;
|
|
aio->command_addr = &priv->ata_regs->tf_command;
|
|
|
|
ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
|
|
|
|
/* activate host */
|
|
return ata_host_activate(host, priv->ata_irq, ata_sff_interrupt, 0,
|
|
&mpc52xx_ata_sht);
|
|
}
|
|
|
|
static struct mpc52xx_ata_priv *
|
|
mpc52xx_ata_remove_one(struct device *dev)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
struct mpc52xx_ata_priv *priv = host->private_data;
|
|
|
|
ata_host_detach(host);
|
|
|
|
return priv;
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
/* OF Platform driver */
|
|
/* ======================================================================== */
|
|
|
|
static int __devinit
|
|
mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
|
|
{
|
|
unsigned int ipb_freq;
|
|
struct resource res_mem;
|
|
int ata_irq = 0;
|
|
struct mpc52xx_ata __iomem *ata_regs;
|
|
struct mpc52xx_ata_priv *priv = NULL;
|
|
int rv, ret, task_irq = 0;
|
|
int mwdma_mask = 0, udma_mask = 0;
|
|
const __be32 *prop;
|
|
int proplen;
|
|
struct bcom_task *dmatsk = NULL;
|
|
|
|
/* Get ipb frequency */
|
|
ipb_freq = mpc5xxx_get_bus_frequency(op->node);
|
|
if (!ipb_freq) {
|
|
dev_err(&op->dev, "could not determine IPB bus frequency\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Get device base address from device tree, request the region
|
|
* and ioremap it. */
|
|
rv = of_address_to_resource(op->node, 0, &res_mem);
|
|
if (rv) {
|
|
dev_err(&op->dev, "could not determine device base address\n");
|
|
return rv;
|
|
}
|
|
|
|
if (!devm_request_mem_region(&op->dev, res_mem.start,
|
|
sizeof(*ata_regs), DRV_NAME)) {
|
|
dev_err(&op->dev, "error requesting register region\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs));
|
|
if (!ata_regs) {
|
|
dev_err(&op->dev, "error mapping device registers\n");
|
|
rv = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
/*
|
|
* By default, all DMA modes are disabled for the MPC5200. Some
|
|
* boards don't have the required signals routed to make DMA work.
|
|
* Also, the MPC5200B has a silicon bug that causes data corruption
|
|
* with UDMA if it is used at the same time as the LocalPlus bus.
|
|
*
|
|
* Instead of trying to guess what modes are usable, check the
|
|
* ATA device tree node to find out what DMA modes work on the board.
|
|
* UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>"
|
|
* to the kernel boot parameters.
|
|
*
|
|
* The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
|
|
* UDMA modes 0, 1 and 2.
|
|
*/
|
|
prop = of_get_property(op->node, "mwdma-mode", &proplen);
|
|
if ((prop) && (proplen >= 4))
|
|
mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
|
|
prop = of_get_property(op->node, "udma-mode", &proplen);
|
|
if ((prop) && (proplen >= 4))
|
|
udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
|
|
|
|
ata_irq = irq_of_parse_and_map(op->node, 0);
|
|
if (ata_irq == NO_IRQ) {
|
|
dev_err(&op->dev, "error mapping irq\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Prepare our private structure */
|
|
priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC);
|
|
if (!priv) {
|
|
dev_err(&op->dev, "error allocating private structure\n");
|
|
rv = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
priv->ipb_period = 1000000000 / (ipb_freq / 1000);
|
|
priv->ata_regs = ata_regs;
|
|
priv->ata_regs_pa = res_mem.start;
|
|
priv->ata_irq = ata_irq;
|
|
priv->csel = -1;
|
|
priv->mpc52xx_ata_dma_last_write = -1;
|
|
|
|
if (ipb_freq/1000000 == 66) {
|
|
priv->mdmaspec = mdmaspec66;
|
|
priv->udmaspec = udmaspec66;
|
|
} else {
|
|
priv->mdmaspec = mdmaspec132;
|
|
priv->udmaspec = udmaspec132;
|
|
}
|
|
|
|
/* Allocate a BestComm task for DMA */
|
|
dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE);
|
|
if (!dmatsk) {
|
|
dev_err(&op->dev, "bestcomm initialization failed\n");
|
|
rv = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
task_irq = bcom_get_task_irq(dmatsk);
|
|
ret = request_irq(task_irq, &mpc52xx_ata_task_irq, IRQF_DISABLED,
|
|
"ATA task", priv);
|
|
if (ret) {
|
|
dev_err(&op->dev, "error requesting DMA IRQ\n");
|
|
goto err;
|
|
}
|
|
priv->dmatsk = dmatsk;
|
|
|
|
/* Init the hw */
|
|
rv = mpc52xx_ata_hw_init(priv);
|
|
if (rv) {
|
|
dev_err(&op->dev, "error initializing hardware\n");
|
|
goto err;
|
|
}
|
|
|
|
/* Register ourselves to libata */
|
|
rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start,
|
|
mwdma_mask, udma_mask);
|
|
if (rv) {
|
|
dev_err(&op->dev, "error registering with ATA layer\n");
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
devm_release_mem_region(&op->dev, res_mem.start, sizeof(*ata_regs));
|
|
if (ata_irq)
|
|
irq_dispose_mapping(ata_irq);
|
|
if (task_irq)
|
|
irq_dispose_mapping(task_irq);
|
|
if (dmatsk)
|
|
bcom_ata_release(dmatsk);
|
|
if (ata_regs)
|
|
devm_iounmap(&op->dev, ata_regs);
|
|
if (priv)
|
|
devm_kfree(&op->dev, priv);
|
|
return rv;
|
|
}
|
|
|
|
static int
|
|
mpc52xx_ata_remove(struct of_device *op)
|
|
{
|
|
struct mpc52xx_ata_priv *priv;
|
|
int task_irq;
|
|
|
|
/* Deregister the ATA interface */
|
|
priv = mpc52xx_ata_remove_one(&op->dev);
|
|
|
|
/* Clean up DMA */
|
|
task_irq = bcom_get_task_irq(priv->dmatsk);
|
|
irq_dispose_mapping(task_irq);
|
|
bcom_ata_release(priv->dmatsk);
|
|
irq_dispose_mapping(priv->ata_irq);
|
|
|
|
/* Clear up IO allocations */
|
|
devm_iounmap(&op->dev, priv->ata_regs);
|
|
devm_release_mem_region(&op->dev, priv->ata_regs_pa,
|
|
sizeof(*priv->ata_regs));
|
|
devm_kfree(&op->dev, priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int
|
|
mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(&op->dev);
|
|
|
|
return ata_host_suspend(host, state);
|
|
}
|
|
|
|
static int
|
|
mpc52xx_ata_resume(struct of_device *op)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(&op->dev);
|
|
struct mpc52xx_ata_priv *priv = host->private_data;
|
|
int rv;
|
|
|
|
rv = mpc52xx_ata_hw_init(priv);
|
|
if (rv) {
|
|
dev_err(host->dev, "error initializing hardware\n");
|
|
return rv;
|
|
}
|
|
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
static struct of_device_id mpc52xx_ata_of_match[] = {
|
|
{ .compatible = "fsl,mpc5200-ata", },
|
|
{ .compatible = "mpc5200-ata", },
|
|
{},
|
|
};
|
|
|
|
|
|
static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = DRV_NAME,
|
|
.match_table = mpc52xx_ata_of_match,
|
|
.probe = mpc52xx_ata_probe,
|
|
.remove = mpc52xx_ata_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = mpc52xx_ata_suspend,
|
|
.resume = mpc52xx_ata_resume,
|
|
#endif
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
|
|
/* ======================================================================== */
|
|
/* Module */
|
|
/* ======================================================================== */
|
|
|
|
static int __init
|
|
mpc52xx_ata_init(void)
|
|
{
|
|
printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
|
|
return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
|
|
}
|
|
|
|
static void __exit
|
|
mpc52xx_ata_exit(void)
|
|
{
|
|
of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
|
|
}
|
|
|
|
module_init(mpc52xx_ata_init);
|
|
module_exit(mpc52xx_ata_exit);
|
|
|
|
MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
|
|
MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
|
|
|