dd5e1339e5
The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. This patch does include the basic support for the fpga device driver, but not the device driver itself. Signed-off-by: Alex Raimondi <mailinglist@miromico.ch> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
35 lines
1.1 KiB
C
35 lines
1.1 KiB
C
/*
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* Clock management for AT32AP CPUs
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Based on arch/arm/mach-at91/clock.c
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/list.h>
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void at32_clk_register(struct clk *clk);
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struct clk {
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struct list_head list; /* linking element */
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const char *name; /* Clock name/function */
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struct device *dev; /* Device the clock is used by */
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struct clk *parent; /* Parent clock, if any */
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void (*mode)(struct clk *clk, int enabled);
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unsigned long (*get_rate)(struct clk *clk);
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long (*set_rate)(struct clk *clk, unsigned long rate,
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int apply);
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int (*set_parent)(struct clk *clk, struct clk *parent);
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u16 users; /* Enabled if non-zero */
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u16 index; /* Sibling index */
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};
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unsigned long pba_clk_get_rate(struct clk *clk);
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void pba_clk_mode(struct clk *clk, int enabled);
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