173d668138
The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
200 lines
5.5 KiB
ArmAsm
200 lines
5.5 KiB
ArmAsm
/*
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* arch/xtensa/kernel/coprocessor.S
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*
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* Xtensa processor configuration-specific table of coprocessor and
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* other custom register layout information.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 - 2005 Tensilica Inc.
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*
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* Marc Gauthier <marc@tensilica.com> <marc@alumni.uwaterloo.ca>
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*/
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/*
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* This module contains a table that describes the layout of the various
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* custom registers and states associated with each coprocessor, as well
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* as those not associated with any coprocessor ("extra state").
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* This table is included with core dumps and is available via the ptrace
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* interface, allowing the layout of such register/state information to
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* be modified in the kernel without affecting the debugger. Each
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* register or state is identified using a 32-bit "libdb target number"
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* assigned when the Xtensa processor is generated.
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*/
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#include <linux/linkage.h>
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#include <asm/processor.h>
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#if XCHAL_HAVE_CP
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#define CP_LAST ((XCHAL_CP_MAX - 1) * COPROCESSOR_INFO_SIZE)
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ENTRY(release_coprocessors)
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entry a1, 16
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# a2: task
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movi a3, 1 << XCHAL_CP_MAX # a3: coprocessor-bit
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movi a4, coprocessor_info+CP_LAST # a4: owner-table
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# a5: tmp
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movi a6, 0 # a6: 0
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rsil a7, LOCKLEVEL # a7: PS
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1: /* Check if task is coprocessor owner of coprocessor[i]. */
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l32i a5, a4, COPROCESSOR_INFO_OWNER
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srli a3, a3, 1
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beqz a3, 1f
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addi a4, a4, -8
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beq a2, a5, 1b
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/* Found an entry: Clear entry CPENABLE bit to disable CP. */
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rsr a5, CPENABLE
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s32i a6, a4, COPROCESSOR_INFO_OWNER
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xor a5, a3, a5
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wsr a5, CPENABLE
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bnez a3, 1b
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1: wsr a7, PS
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rsync
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retw
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ENTRY(disable_coprocessor)
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entry sp, 16
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rsil a7, LOCKLEVEL
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rsr a3, CPENABLE
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movi a4, 1
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ssl a2
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sll a4, a4
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and a4, a3, a4
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xor a3, a3, a4
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wsr a3, CPENABLE
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wsr a7, PS
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rsync
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retw
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ENTRY(enable_coprocessor)
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entry sp, 16
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rsil a7, LOCKLEVEL
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rsr a3, CPENABLE
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movi a4, 1
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ssl a2
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sll a4, a4
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or a3, a3, a4
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wsr a3, CPENABLE
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wsr a7, PS
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rsync
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retw
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ENTRY(save_coprocessor_extra)
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entry sp, 16
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xchal_extra_store_funcbody
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retw
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ENTRY(restore_coprocessor_extra)
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entry sp, 16
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xchal_extra_load_funcbody
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retw
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ENTRY(save_coprocessor_registers)
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entry sp, 16
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xchal_cpi_store_funcbody
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retw
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ENTRY(restore_coprocessor_registers)
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entry sp, 16
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xchal_cpi_load_funcbody
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retw
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/*
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* The Xtensa compile-time HAL (core.h) XCHAL_*_SA_CONTENTS_LIBDB macros
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* describe the contents of coprocessor & extra save areas in terms of
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* undefined CONTENTS_LIBDB_{SREG,UREG,REGF} macros. We define these
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* latter macros here; they expand into a table of the format we want.
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* The general format is:
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*
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* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum,
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* bitmask, rsv2, rsv3)
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* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum,
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* bitmask, rsv2, rsv3)
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* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index,
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* numentries, contentsize, regname_base,
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* regfile_name, rsv2, rsv3)
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*
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* For this table, we only care about the <libdbnum>, <offset> and <size>
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* fields.
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*/
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/* Map all XCHAL CONTENTS macros to the reg_entry asm macro defined below: */
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#define CONTENTS_LIBDB_SREG(libdbnum,offset,size,align,rsv1,name,sregnum, \
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bitmask, rsv2, rsv3) \
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reg_entry libdbnum, offset, size ;
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#define CONTENTS_LIBDB_UREG(libdbnum,offset,size,align,rsv1,name,uregnum, \
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bitmask, rsv2, rsv3) \
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reg_entry libdbnum, offset, size ;
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#define CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, \
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numentries, contentsize, regname_base, \
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regfile_name, rsv2, rsv3) \
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reg_entry libdbnum, offset, size ;
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/* A single table entry: */
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.macro reg_entry libdbnum, offset, size
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.ifne (__last_offset-(__last_group_offset+\offset))
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/* padding entry */
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.word (0xFC000000+__last_offset-(__last_group_offset+\offset))
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.endif
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.word \libdbnum /* actual entry */
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.set __last_offset, __last_group_offset+\offset+\size
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.endm /* reg_entry */
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/* Table entry that marks the beginning of a group (coprocessor or "extra"): */
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.macro reg_group cpnum, num_entries, align
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.set __last_group_offset, (__last_offset + \align- 1) & -\align
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.ifne \num_entries
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.word 0xFD000000+(\cpnum<<16)+\num_entries
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.endif
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.endm /* reg_group */
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/*
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* Register info tables.
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*/
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.section .rodata, "a"
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.globl _xtensa_reginfo_tables
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.globl _xtensa_reginfo_table_size
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.align 4
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_xtensa_reginfo_table_size:
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.word _xtensa_reginfo_table_end - _xtensa_reginfo_tables
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_xtensa_reginfo_tables:
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.set __last_offset, 0
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reg_group 0xFF, XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM, XCHAL_EXTRA_SA_ALIGN
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XCHAL_EXTRA_SA_CONTENTS_LIBDB
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reg_group 0, XCHAL_CP0_SA_CONTENTS_LIBDB_NUM, XCHAL_CP0_SA_ALIGN
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XCHAL_CP0_SA_CONTENTS_LIBDB
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reg_group 1, XCHAL_CP1_SA_CONTENTS_LIBDB_NUM, XCHAL_CP1_SA_ALIGN
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XCHAL_CP1_SA_CONTENTS_LIBDB
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reg_group 2, XCHAL_CP2_SA_CONTENTS_LIBDB_NUM, XCHAL_CP2_SA_ALIGN
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XCHAL_CP2_SA_CONTENTS_LIBDB
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reg_group 3, XCHAL_CP3_SA_CONTENTS_LIBDB_NUM, XCHAL_CP3_SA_ALIGN
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XCHAL_CP3_SA_CONTENTS_LIBDB
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reg_group 4, XCHAL_CP4_SA_CONTENTS_LIBDB_NUM, XCHAL_CP4_SA_ALIGN
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XCHAL_CP4_SA_CONTENTS_LIBDB
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reg_group 5, XCHAL_CP5_SA_CONTENTS_LIBDB_NUM, XCHAL_CP5_SA_ALIGN
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XCHAL_CP5_SA_CONTENTS_LIBDB
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reg_group 6, XCHAL_CP6_SA_CONTENTS_LIBDB_NUM, XCHAL_CP6_SA_ALIGN
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XCHAL_CP6_SA_CONTENTS_LIBDB
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reg_group 7, XCHAL_CP7_SA_CONTENTS_LIBDB_NUM, XCHAL_CP7_SA_ALIGN
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XCHAL_CP7_SA_CONTENTS_LIBDB
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.word 0xFC000000 /* invalid register number,marks end of table*/
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_xtensa_reginfo_table_end:
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#endif
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