c1821c2e97
This provides a noexec protection on s390 hardware. Our hardware does not have any bits left in the pte for a hw noexec bit, so this is a different approach using shadow page tables and a special addressing mode that allows separate address spaces for code and data. As a special feature of our "secondary-space" addressing mode, separate page tables can be specified for the translation of data addresses (storage operands) and instruction addresses. The shadow page table is used for the instruction addresses and the standard page table for the data addresses. The shadow page table is linked to the standard page table by a pointer in page->lru.next of the struct page corresponding to the page that contains the standard page table (since page->private is not really private with the pte_lock and the page table pages are not in the LRU list). Depending on the software bits of a pte, it is either inserted into both page tables or just into the standard (data) page table. Pages of a vma that does not have the VM_EXEC bit set get mapped only in the data address space. Any try to execute code on such a page will cause a page translation exception. The standard reaction to this is a SIGSEGV with two exceptions: the two system call opcodes 0x0a77 (sys_sigreturn) and 0x0aad (sys_rt_sigreturn) are allowed. They are stored by the kernel to the signal stack frame. Unfortunately, the signal return mechanism cannot be modified to use an SA_RESTORER because the exception unwinding code depends on the system call opcode stored behind the signal stack frame. This feature requires that user space is executed in secondary-space mode and the kernel in home-space mode, which means that the addressing modes need to be switched and that the noexec protection only works for user space. After switching the addressing modes, we cannot use the mvcp/mvcs instructions anymore to copy between kernel and user space. A new mvcos instruction has been added to the z9 EC/BC hardware which allows to copy between arbitrary address spaces, but on older hardware the page tables need to be walked manually. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* include/asm-s390/mmu_context.h
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*
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* S390 version
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*
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* Derived from "include/asm-i386/mmu_context.h"
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*/
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#ifndef __S390_MMU_CONTEXT_H
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#define __S390_MMU_CONTEXT_H
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#include <asm/pgalloc.h>
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/*
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* get a new mmu context.. S390 don't know about contexts.
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*/
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#define init_new_context(tsk,mm) 0
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#define destroy_context(mm) do { } while (0)
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#ifndef __s390x__
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#define LCTL_OPCODE "lctl"
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#define PGTABLE_BITS (_SEGMENT_TABLE|USER_STD_MASK)
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#else
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#define LCTL_OPCODE "lctlg"
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#define PGTABLE_BITS (_REGION_TABLE|USER_STD_MASK)
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#endif
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static inline void enter_lazy_tlb(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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pgd_t *shadow_pgd = get_shadow_pgd(next->pgd);
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if (prev != next) {
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S390_lowcore.user_asce = (__pa(next->pgd) & PAGE_MASK) |
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PGTABLE_BITS;
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if (shadow_pgd) {
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/* Load primary/secondary space page table origin. */
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S390_lowcore.user_exec_asce =
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(__pa(shadow_pgd) & PAGE_MASK) | PGTABLE_BITS;
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asm volatile(LCTL_OPCODE" 1,1,%0\n"
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LCTL_OPCODE" 7,7,%1"
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: : "m" (S390_lowcore.user_exec_asce),
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"m" (S390_lowcore.user_asce) );
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} else if (switch_amode) {
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/* Load primary space page table origin. */
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asm volatile(LCTL_OPCODE" 1,1,%0"
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: : "m" (S390_lowcore.user_asce) );
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} else
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/* Load home space page table origin. */
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asm volatile(LCTL_OPCODE" 13,13,%0"
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: : "m" (S390_lowcore.user_asce) );
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}
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cpu_set(smp_processor_id(), next->cpu_vm_mask);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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static inline void activate_mm(struct mm_struct *prev,
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struct mm_struct *next)
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{
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switch_mm(prev, next, current);
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set_fs(current->thread.mm_segment);
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}
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#endif /* __S390_MMU_CONTEXT_H */
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