84c493d8e1
Fix, complete, and indent IP32 parport definitions.
Definition were wrong for CTXINUSE and DMACTIVE (1-bit shift).
Add macros DATA_BOUND, DATALEN_SHIFT, and CTRSHIFT.
Signed-off-by: Arnaud Giersch <arnaud.giersch@free.fr>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
368 lines
11 KiB
C
368 lines
11 KiB
C
/*
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* Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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* Copyright (C) 2004 Ladislav Michl
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*/
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#ifndef __ASM_MACE_H__
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#define __ASM_MACE_H__
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/*
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* Address map
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*/
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#define MACE_BASE 0x1f000000 /* physical */
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#undef BIT
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#define BIT(x) (1UL << (x))
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/*
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* PCI interface
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*/
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struct mace_pci {
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volatile unsigned int error_addr;
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volatile unsigned int error;
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#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
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#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
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#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
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#define MACEPCI_ERROR_RETRY_ERR BIT(28)
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#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
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#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
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#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
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#define MACEPCI_ERROR_PARITY_ERR BIT(24)
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#define MACEPCI_ERROR_OVERRUN BIT(23)
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#define MACEPCI_ERROR_RSVD BIT(22)
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#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
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#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
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#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
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#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
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#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
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#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
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#define MACEPCI_ERROR_SIG_TABORT BIT(4)
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#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
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#define MACEPCI_ERROR_DEVSEL_FAST 0
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#define MACEPCI_ERROR_DEVSEL_MED 0x40
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#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
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#define MACEPCI_ERROR_FBB BIT(1)
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#define MACEPCI_ERROR_66MHZ BIT(0)
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volatile unsigned int control;
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#define MACEPCI_CONTROL_INT(x) BIT(x)
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#define MACEPCI_CONTROL_INT_MASK 0xff
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#define MACEPCI_CONTROL_SERR_ENA BIT(8)
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#define MACEPCI_CONTROL_ARB_N6 BIT(9)
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#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
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#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
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#define MACEPCI_CONTROL_ARB_N3 BIT(12)
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#define MACEPCI_CONTROL_ARB_N4 BIT(13)
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#define MACEPCI_CONTROL_ARB_N5 BIT(14)
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#define MACEPCI_CONTROL_PARK_LIU BIT(15)
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#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
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#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
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#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
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#define MACEPCI_CONTROL_PARITY_INT BIT(25)
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#define MACEPCI_CONTROL_SERR_INT BIT(26)
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#define MACEPCI_CONTROL_IT_INT BIT(27)
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#define MACEPCI_CONTROL_RE_INT BIT(28)
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#define MACEPCI_CONTROL_DPED_INT BIT(29)
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#define MACEPCI_CONTROL_TAR_INT BIT(30)
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#define MACEPCI_CONTROL_MAR_INT BIT(31)
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volatile unsigned int rev;
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unsigned int _pad[0xcf8/4 - 4];
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volatile unsigned int config_addr;
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union {
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volatile unsigned char b[4];
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volatile unsigned short w[2];
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volatile unsigned int l;
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} config_data;
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};
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#define MACEPCI_LOW_MEMORY 0x1a000000
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#define MACEPCI_LOW_IO 0x18000000
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#define MACEPCI_SWAPPED_VIEW 0
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#define MACEPCI_NATIVE_VIEW 0x40000000
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#define MACEPCI_IO 0x80000000
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#define MACEPCI_HI_MEMORY 0x280000000
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#define MACEPCI_HI_IO 0x100000000
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/*
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* Video interface
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*/
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struct mace_video {
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unsigned long xxx; /* later... */
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};
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/*
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* Ethernet interface
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*/
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struct mace_ethernet {
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volatile unsigned long mac_ctrl;
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volatile unsigned long int_stat;
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volatile unsigned long dma_ctrl;
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volatile unsigned long timer;
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volatile unsigned long tx_int_al;
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volatile unsigned long rx_int_al;
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volatile unsigned long tx_info;
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volatile unsigned long tx_info_al;
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volatile unsigned long rx_buff;
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volatile unsigned long rx_buff_al1;
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volatile unsigned long rx_buff_al2;
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volatile unsigned long diag;
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volatile unsigned long phy_data;
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volatile unsigned long phy_regs;
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volatile unsigned long phy_trans_go;
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volatile unsigned long backoff_seed;
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/*===================================*/
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volatile unsigned long imq_reserved[4];
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volatile unsigned long mac_addr;
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volatile unsigned long mac_addr2;
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volatile unsigned long mcast_filter;
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volatile unsigned long tx_ring_base;
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/* Following are read-only registers for debugging */
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volatile unsigned long tx_pkt1_hdr;
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volatile unsigned long tx_pkt1_ptr[3];
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volatile unsigned long tx_pkt2_hdr;
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volatile unsigned long tx_pkt2_ptr[3];
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/*===================================*/
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volatile unsigned long rx_fifo;
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};
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/*
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* Peripherals
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*/
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/* Audio registers */
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struct mace_audio {
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volatile unsigned long control;
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volatile unsigned long codec_control; /* codec status control */
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volatile unsigned long codec_mask; /* codec status input mask */
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volatile unsigned long codec_read; /* codec status read data */
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struct {
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volatile unsigned long control; /* channel control */
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volatile unsigned long read_ptr; /* channel read pointer */
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volatile unsigned long write_ptr; /* channel write pointer */
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volatile unsigned long depth; /* channel depth */
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} chan[3];
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};
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/* register definitions for parallel port DMA */
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struct mace_parport {
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/* 0 - do nothing,
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* 1 - pulse terminal count to the device after buffer is drained */
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#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
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/* Should not cross 4K page boundary */
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#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL
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#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL
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#define MACEPAR_CONTEXT_DATALEN_SHIFT 32
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/* Can be arbitrarily aligned on any byte boundary on output,
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* 64 byte aligned on input */
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#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL
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volatile u64 context_a;
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volatile u64 context_b;
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/* 0 - mem->device, 1 - device->mem */
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#define MACEPAR_CTLSTAT_DIRECTION BIT(0)
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/* 0 - channel frozen, 1 - channel enabled */
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#define MACEPAR_CTLSTAT_ENABLE BIT(1)
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/* 0 - channel active, 1 - complete channel reset */
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#define MACEPAR_CTLSTAT_RESET BIT(2)
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#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
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#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
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volatile u64 cntlstat; /* Control/Status register */
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#define MACEPAR_DIAG_CTXINUSE BIT(0)
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/* 1 - Dma engine is enabled and processing something */
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#define MACEPAR_DIAG_DMACTIVE BIT(1)
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/* Counter of bytes left */
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#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL
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#define MACEPAR_DIAG_CTRSHIFT 2
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volatile u64 diagnostic; /* RO: diagnostic register */
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};
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/* ISA Control and DMA registers */
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struct mace_isactrl {
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volatile unsigned long ringbase;
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#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
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volatile unsigned long misc;
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#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
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#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
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#define MACEISA_NIC_DEASSERT BIT(2)
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#define MACEISA_NIC_DATA BIT(3)
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#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
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#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
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#define MACEISA_DP_RAM_ENABLE BIT(6)
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volatile unsigned long istat;
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volatile unsigned long imask;
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#define MACEISA_AUDIO_SW_INT BIT(0)
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#define MACEISA_AUDIO_SC_INT BIT(1)
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#define MACEISA_AUDIO1_DMAT_INT BIT(2)
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#define MACEISA_AUDIO1_OF_INT BIT(3)
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#define MACEISA_AUDIO2_DMAT_INT BIT(4)
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#define MACEISA_AUDIO2_MERR_INT BIT(5)
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#define MACEISA_AUDIO3_DMAT_INT BIT(6)
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#define MACEISA_AUDIO3_MERR_INT BIT(7)
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#define MACEISA_RTC_INT BIT(8)
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#define MACEISA_KEYB_INT BIT(9)
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#define MACEISA_KEYB_POLL_INT BIT(10)
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#define MACEISA_MOUSE_INT BIT(11)
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#define MACEISA_MOUSE_POLL_INT BIT(12)
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#define MACEISA_TIMER0_INT BIT(13)
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#define MACEISA_TIMER1_INT BIT(14)
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#define MACEISA_TIMER2_INT BIT(15)
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#define MACEISA_PARALLEL_INT BIT(16)
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#define MACEISA_PAR_CTXA_INT BIT(17)
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#define MACEISA_PAR_CTXB_INT BIT(18)
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#define MACEISA_PAR_MERR_INT BIT(19)
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#define MACEISA_SERIAL1_INT BIT(20)
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#define MACEISA_SERIAL1_TDMAT_INT BIT(21)
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#define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
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#define MACEISA_SERIAL1_TDMAME_INT BIT(23)
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#define MACEISA_SERIAL1_RDMAT_INT BIT(24)
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#define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
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#define MACEISA_SERIAL2_INT BIT(26)
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#define MACEISA_SERIAL2_TDMAT_INT BIT(27)
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#define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
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#define MACEISA_SERIAL2_TDMAME_INT BIT(29)
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#define MACEISA_SERIAL2_RDMAT_INT BIT(30)
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#define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
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volatile unsigned long _pad[0x2000/8 - 4];
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volatile unsigned long dp_ram[0x400];
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struct mace_parport parport;
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};
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/* Keyboard & Mouse registers
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* -> drivers/input/serio/maceps2.c */
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struct mace_ps2port {
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volatile unsigned long tx;
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volatile unsigned long rx;
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volatile unsigned long control;
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volatile unsigned long status;
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};
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struct mace_ps2 {
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struct mace_ps2port keyb;
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struct mace_ps2port mouse;
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};
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/* I2C registers
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* -> drivers/i2c/algos/i2c-algo-sgi.c */
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struct mace_i2c {
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volatile unsigned long config;
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#define MACEI2C_RESET BIT(0)
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#define MACEI2C_FAST BIT(1)
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#define MACEI2C_DATA_OVERRIDE BIT(2)
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#define MACEI2C_CLOCK_OVERRIDE BIT(3)
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#define MACEI2C_DATA_STATUS BIT(4)
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#define MACEI2C_CLOCK_STATUS BIT(5)
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volatile unsigned long control;
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volatile unsigned long data;
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};
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/* Timer registers */
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typedef union {
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volatile unsigned long ust_msc;
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struct reg {
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volatile unsigned int ust;
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volatile unsigned int msc;
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} reg;
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} timer_reg;
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struct mace_timers {
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volatile unsigned long ust;
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#define MACE_UST_PERIOD_NS 960
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volatile unsigned long compare1;
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volatile unsigned long compare2;
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volatile unsigned long compare3;
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timer_reg audio_in;
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timer_reg audio_out1;
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timer_reg audio_out2;
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timer_reg video_in1;
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timer_reg video_in2;
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timer_reg video_out;
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};
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struct mace_perif {
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struct mace_audio audio;
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char _pad0[0x10000 - sizeof(struct mace_audio)];
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struct mace_isactrl ctrl;
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char _pad1[0x10000 - sizeof(struct mace_isactrl)];
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struct mace_ps2 ps2;
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char _pad2[0x10000 - sizeof(struct mace_ps2)];
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struct mace_i2c i2c;
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char _pad3[0x10000 - sizeof(struct mace_i2c)];
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struct mace_timers timers;
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char _pad4[0x10000 - sizeof(struct mace_timers)];
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};
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/*
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* ISA peripherals
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*/
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/* Parallel port */
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struct mace_parallel {
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};
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struct mace_ecp1284 { /* later... */
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};
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/* Serial port */
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struct mace_serial {
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volatile unsigned long xxx; /* later... */
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};
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struct mace_isa {
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struct mace_parallel parallel;
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char _pad1[0x8000 - sizeof(struct mace_parallel)];
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struct mace_ecp1284 ecp1284;
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char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
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struct mace_serial serial1;
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char _pad3[0x8000 - sizeof(struct mace_serial)];
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struct mace_serial serial2;
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char _pad4[0x8000 - sizeof(struct mace_serial)];
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volatile unsigned char rtc[0x10000];
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};
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struct sgi_mace {
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char _reserved[0x80000];
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struct mace_pci pci;
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char _pad0[0x80000 - sizeof(struct mace_pci)];
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struct mace_video video_in1;
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char _pad1[0x80000 - sizeof(struct mace_video)];
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struct mace_video video_in2;
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char _pad2[0x80000 - sizeof(struct mace_video)];
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struct mace_video video_out;
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char _pad3[0x80000 - sizeof(struct mace_video)];
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struct mace_ethernet eth;
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char _pad4[0x80000 - sizeof(struct mace_ethernet)];
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struct mace_perif perif;
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char _pad5[0x80000 - sizeof(struct mace_perif)];
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struct mace_isa isa;
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char _pad6[0x80000 - sizeof(struct mace_isa)];
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};
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extern struct sgi_mace *mace;
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#endif /* __ASM_MACE_H__ */
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