8d20a541b0
Patches to support SMP. * Each CPU has its own current_pgd. * flush_tlb_range is implemented as flush_tlb_mm. * Atomic operations implemented with spinlocks. * Semaphores implemented with spinlocks. Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/*
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* linux/arch/cris/mm/fault.c
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*
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* Low level bus fault handler
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*
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*
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* Copyright (C) 2000, 2001 Axis Communications AB
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*
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* Authors: Bjorn Wesen
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*
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*/
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#include <linux/mm.h>
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#include <asm/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/arch/svinto.h>
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#include <asm/mmu_context.h>
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/* debug of low-level TLB reload */
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#undef DEBUG
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#ifdef DEBUG
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#define D(x) x
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#else
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#define D(x)
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#endif
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extern const struct exception_table_entry
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*search_exception_tables(unsigned long addr);
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asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
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int protection, int writeaccess);
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/* fast TLB-fill fault handler
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* this is called from entry.S with interrupts disabled
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*/
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void
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handle_mmu_bus_fault(struct pt_regs *regs)
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{
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int cause;
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int select;
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#ifdef DEBUG
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int index;
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int page_id;
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int acc, inv;
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#endif
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pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
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pmd_t *pmd;
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pte_t pte;
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int miss, we, writeac;
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unsigned long address;
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unsigned long flags;
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cause = *R_MMU_CAUSE;
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address = cause & PAGE_MASK; /* get faulting address */
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select = *R_TLB_SELECT;
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#ifdef DEBUG
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page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
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acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
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inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
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index = IO_EXTRACT(R_TLB_SELECT, index, select);
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#endif
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miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
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we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause);
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writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause);
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D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
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regs->irp, address, miss, inv, we, acc, index, page_id));
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/* leave it to the MM system fault handler */
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if (miss)
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do_page_fault(address, regs, 0, writeac);
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else
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do_page_fault(address, regs, 1, we);
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/* Reload TLB with new entry to avoid an extra miss exception.
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* do_page_fault may have flushed the TLB so we have to restore
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* the MMU registers.
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*/
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local_save_flags(flags);
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local_irq_disable();
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pmd = (pmd_t *)(pgd + pgd_index(address));
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if (pmd_none(*pmd))
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return;
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pte = *pte_offset_kernel(pmd, address);
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if (!pte_present(pte))
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return;
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*R_TLB_SELECT = select;
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*R_TLB_HI = cause;
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*R_TLB_LO = pte_val(pte);
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local_irq_restore(flags);
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}
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