046e26a8ba
The individual SBUS IOMMU arch code now sets the IOMMU information directly into the OF device objects. Signed-off-by: David S. Miller <davem@davemloft.net>
99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/* irq.h: IRQ registers on the 64-bit Sparc.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#ifndef _SPARC64_IRQ_H
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#define _SPARC64_IRQ_H
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/pil.h>
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#include <asm/ptrace.h>
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/* IMAP/ICLR register defines */
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#define IMAP_VALID 0x80000000UL /* IRQ Enabled */
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#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */
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#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */
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#define IMAP_TID_SHIFT 26
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#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */
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#define IMAP_AID_SHIFT 26
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#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */
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#define IMAP_NID_SHIFT 21
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#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */
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#define IMAP_INO 0x0000003fUL /* IRQ Number */
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#define IMAP_INR 0x000007ffUL /* Full interrupt number*/
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#define ICLR_IDLE 0x00000000UL /* Idle state */
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#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */
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#define ICLR_PENDING 0x00000003UL /* Pending state */
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/* The largest number of unique interrupt sources we support.
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* If this needs to ever be larger than 255, you need to change
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* the type of ino_bucket->virt_irq as appropriate.
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*
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* ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
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*/
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#define NR_IRQS 255
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extern void irq_install_pre_handler(int virt_irq,
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void (*func)(unsigned int, void *, void *),
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void *arg1, void *arg2);
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#define irq_canonicalize(irq) (irq)
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extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
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extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
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extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
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extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
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unsigned int msi_devino_start,
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unsigned int msi_devino_end);
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extern void sun4v_destroy_msi(unsigned int virt_irq);
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extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
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unsigned int msi_devino_start,
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unsigned int msi_devino_end,
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unsigned long imap_base,
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unsigned long iclr_base);
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extern void sun4u_destroy_msi(unsigned int virt_irq);
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extern unsigned char virt_irq_alloc(unsigned int dev_handle,
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unsigned int dev_ino);
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#ifdef CONFIG_PCI_MSI
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extern void virt_irq_free(unsigned int virt_irq);
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#endif
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extern void __init init_IRQ(void);
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extern void fixup_irqs(void);
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static inline void set_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%set_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static inline void clear_softint(unsigned long bits)
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{
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__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
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: /* No outputs */
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: "r" (bits));
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}
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static inline unsigned long get_softint(void)
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{
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unsigned long retval;
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__asm__ __volatile__("rd %%softint, %0"
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: "=r" (retval));
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return retval;
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}
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void __trigger_all_cpu_backtrace(void);
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#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
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extern void *hardirq_stack[NR_CPUS];
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extern void *softirq_stack[NR_CPUS];
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#define __ARCH_HAS_DO_SOFTIRQ
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#endif
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