424 lines
18 KiB
Text
424 lines
18 KiB
Text
DMAengine controller documentation
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==================================
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Hardware Introduction
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+++++++++++++++++++++
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Most of the Slave DMA controllers have the same general principles of
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operations.
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They have a given number of channels to use for the DMA transfers, and
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a given number of requests lines.
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Requests and channels are pretty much orthogonal. Channels can be used
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to serve several to any requests. To simplify, channels are the
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entities that will be doing the copy, and requests what endpoints are
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involved.
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The request lines actually correspond to physical lines going from the
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DMA-eligible devices to the controller itself. Whenever the device
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will want to start a transfer, it will assert a DMA request (DRQ) by
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asserting that request line.
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A very simple DMA controller would only take into account a single
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parameter: the transfer size. At each clock cycle, it would transfer a
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byte of data from one buffer to another, until the transfer size has
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been reached.
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That wouldn't work well in the real world, since slave devices might
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require a specific number of bits to be transferred in a single
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cycle. For example, we may want to transfer as much data as the
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physical bus allows to maximize performances when doing a simple
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memory copy operation, but our audio device could have a narrower FIFO
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that requires data to be written exactly 16 or 24 bits at a time. This
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is why most if not all of the DMA controllers can adjust this, using a
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parameter called the transfer width.
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Moreover, some DMA controllers, whenever the RAM is used as a source
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or destination, can group the reads or writes in memory into a buffer,
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so instead of having a lot of small memory accesses, which is not
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really efficient, you'll get several bigger transfers. This is done
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using a parameter called the burst size, that defines how many single
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reads/writes it's allowed to do without the controller splitting the
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transfer into smaller sub-transfers.
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Our theoretical DMA controller would then only be able to do transfers
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that involve a single contiguous block of data. However, some of the
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transfers we usually have are not, and want to copy data from
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non-contiguous buffers to a contiguous buffer, which is called
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scatter-gather.
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DMAEngine, at least for mem2dev transfers, require support for
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scatter-gather. So we're left with two cases here: either we have a
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quite simple DMA controller that doesn't support it, and we'll have to
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implement it in software, or we have a more advanced DMA controller,
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that implements in hardware scatter-gather.
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The latter are usually programmed using a collection of chunks to
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transfer, and whenever the transfer is started, the controller will go
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over that collection, doing whatever we programmed there.
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This collection is usually either a table or a linked list. You will
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then push either the address of the table and its number of elements,
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or the first item of the list to one channel of the DMA controller,
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and whenever a DRQ will be asserted, it will go through the collection
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to know where to fetch the data from.
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Either way, the format of this collection is completely dependent on
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your hardware. Each DMA controller will require a different structure,
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but all of them will require, for every chunk, at least the source and
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destination addresses, whether it should increment these addresses or
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not and the three parameters we saw earlier: the burst size, the
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transfer width and the transfer size.
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The one last thing is that usually, slave devices won't issue DRQ by
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default, and you have to enable this in your slave device driver first
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whenever you're willing to use DMA.
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These were just the general memory-to-memory (also called mem2mem) or
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memory-to-device (mem2dev) kind of transfers. Most devices often
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support other kind of transfers or memory operations that dmaengine
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support and will be detailed later in this document.
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DMA Support in Linux
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++++++++++++++++++++
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Historically, DMA controller drivers have been implemented using the
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async TX API, to offload operations such as memory copy, XOR,
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cryptography, etc., basically any memory to memory operation.
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Over time, the need for memory to device transfers arose, and
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dmaengine was extended. Nowadays, the async TX API is written as a
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layer on top of dmaengine, and acts as a client. Still, dmaengine
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accommodates that API in some cases, and made some design choices to
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ensure that it stayed compatible.
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For more information on the Async TX API, please look the relevant
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documentation file in Documentation/crypto/async-tx-api.txt.
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DMAEngine Registration
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++++++++++++++++++++++
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struct dma_device Initialization
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--------------------------------
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Just like any other kernel framework, the whole DMAEngine registration
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relies on the driver filling a structure and registering against the
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framework. In our case, that structure is dma_device.
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The first thing you need to do in your driver is to allocate this
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structure. Any of the usual memory allocators will do, but you'll also
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need to initialize a few fields in there:
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* channels: should be initialized as a list using the
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INIT_LIST_HEAD macro for example
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* src_addr_widths:
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- should contain a bitmask of the supported source transfer width
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* dst_addr_widths:
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- should contain a bitmask of the supported destination transfer
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width
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* directions:
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- should contain a bitmask of the supported slave directions
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(i.e. excluding mem2mem transfers)
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* residue_granularity:
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- Granularity of the transfer residue reported to dma_set_residue.
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- This can be either:
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+ Descriptor
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-> Your device doesn't support any kind of residue
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reporting. The framework will only know that a particular
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transaction descriptor is done.
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+ Segment
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-> Your device is able to report which chunks have been
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transferred
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+ Burst
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-> Your device is able to report which burst have been
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transferred
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* dev: should hold the pointer to the struct device associated
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to your current driver instance.
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Supported transaction types
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---------------------------
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The next thing you need is to set which transaction types your device
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(and driver) supports.
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Our dma_device structure has a field called cap_mask that holds the
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various types of transaction supported, and you need to modify this
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mask using the dma_cap_set function, with various flags depending on
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transaction types you support as an argument.
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All those capabilities are defined in the dma_transaction_type enum,
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in include/linux/dmaengine.h
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Currently, the types available are:
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* DMA_MEMCPY
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- The device is able to do memory to memory copies
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* DMA_XOR
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- The device is able to perform XOR operations on memory areas
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- Used to accelerate XOR intensive tasks, such as RAID5
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* DMA_XOR_VAL
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- The device is able to perform parity check using the XOR
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algorithm against a memory buffer.
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* DMA_PQ
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- The device is able to perform RAID6 P+Q computations, P being a
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simple XOR, and Q being a Reed-Solomon algorithm.
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* DMA_PQ_VAL
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- The device is able to perform parity check using RAID6 P+Q
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algorithm against a memory buffer.
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* DMA_INTERRUPT
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- The device is able to trigger a dummy transfer that will
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generate periodic interrupts
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- Used by the client drivers to register a callback that will be
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called on a regular basis through the DMA controller interrupt
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* DMA_SG
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- The device supports memory to memory scatter-gather
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transfers.
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- Even though a plain memcpy can look like a particular case of a
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scatter-gather transfer, with a single chunk to transfer, it's a
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distinct transaction type in the mem2mem transfers case
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* DMA_PRIVATE
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- The devices only supports slave transfers, and as such isn't
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available for async transfers.
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* DMA_ASYNC_TX
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- Must not be set by the device, and will be set by the framework
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if needed
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- /* TODO: What is it about? */
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* DMA_SLAVE
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- The device can handle device to memory transfers, including
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scatter-gather transfers.
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- While in the mem2mem case we were having two distinct types to
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deal with a single chunk to copy or a collection of them, here,
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we just have a single transaction type that is supposed to
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handle both.
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- If you want to transfer a single contiguous memory buffer,
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simply build a scatter list with only one item.
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* DMA_CYCLIC
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- The device can handle cyclic transfers.
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- A cyclic transfer is a transfer where the chunk collection will
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loop over itself, with the last item pointing to the first.
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- It's usually used for audio transfers, where you want to operate
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on a single ring buffer that you will fill with your audio data.
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* DMA_INTERLEAVE
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- The device supports interleaved transfer.
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- These transfers can transfer data from a non-contiguous buffer
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to a non-contiguous buffer, opposed to DMA_SLAVE that can
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transfer data from a non-contiguous data set to a continuous
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destination buffer.
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- It's usually used for 2d content transfers, in which case you
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want to transfer a portion of uncompressed data directly to the
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display to print it
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These various types will also affect how the source and destination
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addresses change over time.
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Addresses pointing to RAM are typically incremented (or decremented)
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after each transfer. In case of a ring buffer, they may loop
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(DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)
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are typically fixed.
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Device operations
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-----------------
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Our dma_device structure also requires a few function pointers in
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order to implement the actual logic, now that we described what
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operations we were able to perform.
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The functions that we have to fill in there, and hence have to
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implement, obviously depend on the transaction types you reported as
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supported.
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* device_alloc_chan_resources
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* device_free_chan_resources
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- These functions will be called whenever a driver will call
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dma_request_channel or dma_release_channel for the first/last
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time on the channel associated to that driver.
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- They are in charge of allocating/freeing all the needed
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resources in order for that channel to be useful for your
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driver.
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- These functions can sleep.
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* device_prep_dma_*
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- These functions are matching the capabilities you registered
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previously.
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- These functions all take the buffer or the scatterlist relevant
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for the transfer being prepared, and should create a hardware
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descriptor or a list of hardware descriptors from it
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- These functions can be called from an interrupt context
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- Any allocation you might do should be using the GFP_NOWAIT
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flag, in order not to potentially sleep, but without depleting
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the emergency pool either.
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- Drivers should try to pre-allocate any memory they might need
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during the transfer setup at probe time to avoid putting to
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much pressure on the nowait allocator.
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- It should return a unique instance of the
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dma_async_tx_descriptor structure, that further represents this
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particular transfer.
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- This structure can be initialized using the function
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dma_async_tx_descriptor_init.
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- You'll also need to set two fields in this structure:
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+ flags:
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TODO: Can it be modified by the driver itself, or
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should it be always the flags passed in the arguments
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+ tx_submit: A pointer to a function you have to implement,
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that is supposed to push the current
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transaction descriptor to a pending queue, waiting
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for issue_pending to be called.
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- In this structure the function pointer callback_result can be
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initialized in order for the submitter to be notified that a
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transaction has completed. In the earlier code the function pointer
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callback has been used. However it does not provide any status to the
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transaction and will be deprecated. The result structure defined as
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dmaengine_result that is passed in to callback_result has two fields:
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+ result: This provides the transfer result defined by
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dmaengine_tx_result. Either success or some error
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condition.
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+ residue: Provides the residue bytes of the transfer for those that
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support residue.
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* device_issue_pending
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- Takes the first transaction descriptor in the pending queue,
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and starts the transfer. Whenever that transfer is done, it
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should move to the next transaction in the list.
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- This function can be called in an interrupt context
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* device_tx_status
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- Should report the bytes left to go over on the given channel
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- Should only care about the transaction descriptor passed as
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argument, not the currently active one on a given channel
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- The tx_state argument might be NULL
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- Should use dma_set_residue to report it
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- In the case of a cyclic transfer, it should only take into
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account the current period.
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- This function can be called in an interrupt context.
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* device_config
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- Reconfigures the channel with the configuration given as
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argument
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- This command should NOT perform synchronously, or on any
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currently queued transfers, but only on subsequent ones
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- In this case, the function will receive a dma_slave_config
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structure pointer as an argument, that will detail which
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configuration to use.
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- Even though that structure contains a direction field, this
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field is deprecated in favor of the direction argument given to
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the prep_* functions
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- This call is mandatory for slave operations only. This should NOT be
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set or expected to be set for memcpy operations.
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If a driver support both, it should use this call for slave
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operations only and not for memcpy ones.
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* device_pause
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- Pauses a transfer on the channel
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- This command should operate synchronously on the channel,
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pausing right away the work of the given channel
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* device_resume
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- Resumes a transfer on the channel
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- This command should operate synchronously on the channel,
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resuming right away the work of the given channel
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* device_terminate_all
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- Aborts all the pending and ongoing transfers on the channel
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- For aborted transfers the complete callback should not be called
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- Can be called from atomic context or from within a complete
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callback of a descriptor. Must not sleep. Drivers must be able
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to handle this correctly.
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- Termination may be asynchronous. The driver does not have to
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wait until the currently active transfer has completely stopped.
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See device_synchronize.
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* device_synchronize
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- Must synchronize the termination of a channel to the current
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context.
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- Must make sure that memory for previously submitted
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descriptors is no longer accessed by the DMA controller.
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- Must make sure that all complete callbacks for previously
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submitted descriptors have finished running and none are
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scheduled to run.
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- May sleep.
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Misc notes (stuff that should be documented, but don't really know
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where to put them)
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------------------------------------------------------------------
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* dma_run_dependencies
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- Should be called at the end of an async TX transfer, and can be
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ignored in the slave transfers case.
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- Makes sure that dependent operations are run before marking it
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as complete.
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* dma_cookie_t
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- it's a DMA transaction ID that will increment over time.
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- Not really relevant any more since the introduction of virt-dma
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that abstracts it away.
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* DMA_CTRL_ACK
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- If clear, the descriptor cannot be reused by provider until the
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client acknowledges receipt, i.e. has has a chance to establish any
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dependency chains
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- This can be acked by invoking async_tx_ack()
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- If set, does not mean descriptor can be reused
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* DMA_CTRL_REUSE
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- If set, the descriptor can be reused after being completed. It should
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not be freed by provider if this flag is set.
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- The descriptor should be prepared for reuse by invoking
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dmaengine_desc_set_reuse() which will set DMA_CTRL_REUSE.
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- dmaengine_desc_set_reuse() will succeed only when channel support
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reusable descriptor as exhibited by capabilities
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- As a consequence, if a device driver wants to skip the dma_map_sg() and
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dma_unmap_sg() in between 2 transfers, because the DMA'd data wasn't used,
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it can resubmit the transfer right after its completion.
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- Descriptor can be freed in few ways
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- Clearing DMA_CTRL_REUSE by invoking dmaengine_desc_clear_reuse()
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and submitting for last txn
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- Explicitly invoking dmaengine_desc_free(), this can succeed only
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when DMA_CTRL_REUSE is already set
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- Terminating the channel
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General Design Notes
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--------------------
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Most of the DMAEngine drivers you'll see are based on a similar design
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that handles the end of transfer interrupts in the handler, but defer
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most work to a tasklet, including the start of a new transfer whenever
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the previous transfer ended.
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This is a rather inefficient design though, because the inter-transfer
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latency will be not only the interrupt latency, but also the
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scheduling latency of the tasklet, which will leave the channel idle
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in between, which will slow down the global transfer rate.
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You should avoid this kind of practice, and instead of electing a new
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transfer in your tasklet, move that part to the interrupt handler in
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order to have a shorter idle window (that we can't really avoid
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anyway).
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Glossary
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--------
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Burst: A number of consecutive read or write operations
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that can be queued to buffers before being flushed to
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memory.
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Chunk: A contiguous collection of bursts
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Transfer: A collection of chunks (be it contiguous or not)
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