a50808b6c4
Add register definitions for Freescale STMP 378n boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
102 lines
3.7 KiB
C
102 lines
3.7 KiB
C
/*
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* stmp378x: SSP register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
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#define REGS_SSP1_PHYS 0x80010000
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#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
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#define REGS_SSP2_PHYS 0x80034000
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#define REGS_SSP_SIZE 0x2000
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#define HW_SSP_CTRL0 0x0
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#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
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#define BP_SSP_CTRL0_XFER_COUNT 0
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#define BM_SSP_CTRL0_ENABLE 0x00010000
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#define BM_SSP_CTRL0_GET_RESP 0x00020000
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#define BM_SSP_CTRL0_LONG_RESP 0x00080000
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#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
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#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
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#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
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#define BP_SSP_CTRL0_BUS_WIDTH 22
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#define BM_SSP_CTRL0_DATA_XFER 0x01000000
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#define BM_SSP_CTRL0_READ 0x02000000
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#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
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#define BM_SSP_CTRL0_LOCK_CS 0x08000000
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#define BM_SSP_CTRL0_RUN 0x20000000
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#define BM_SSP_CTRL0_CLKGATE 0x40000000
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#define BM_SSP_CTRL0_SFTRST 0x80000000
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#define HW_SSP_CMD0 0x10
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#define BM_SSP_CMD0_CMD 0x000000FF
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#define BP_SSP_CMD0_CMD 0
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#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
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#define BP_SSP_CMD0_BLOCK_COUNT 8
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#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
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#define BP_SSP_CMD0_BLOCK_SIZE 16
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#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
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#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
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#define BP_SSP_CMD1_CMD_ARG 0
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#define HW_SSP_TIMING 0x50
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#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
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#define BP_SSP_TIMING_CLOCK_RATE 0
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#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
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#define BP_SSP_TIMING_CLOCK_DIVIDE 8
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#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
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#define BP_SSP_TIMING_TIMEOUT 16
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#define HW_SSP_CTRL1 0x60
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#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
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#define BP_SSP_CTRL1_SSP_MODE 0
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#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
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#define BP_SSP_CTRL1_WORD_LENGTH 4
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#define BM_SSP_CTRL1_POLARITY 0x00000200
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#define BM_SSP_CTRL1_PHASE 0x00000400
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#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
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#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
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#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
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#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
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#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
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#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
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#define HW_SSP_DATA 0x70
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#define HW_SSP_SDRESP0 0x80
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#define HW_SSP_SDRESP1 0x90
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#define HW_SSP_SDRESP2 0xA0
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#define HW_SSP_SDRESP3 0xB0
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#define HW_SSP_STATUS 0xC0
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#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
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#define BM_SSP_STATUS_TIMEOUT 0x00001000
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#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
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#define BM_SSP_STATUS_RESP_ERR 0x00008000
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#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
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#define BM_SSP_STATUS_CARD_DETECT 0x10000000
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