c8c99699bd
Determine cache size required per McBSP port at init time, based on processor type running on. Allocate space for storing cached copies of McBSP register values at port request. Modify omap_msbcp_write() function to update the cache with every register write operation. Modify omap_mcbsp_read() to support reading from cache or hardware. Update MCBSP_READ() macro for modified omap_mcbsp_read() function API. Introduce a new macro that reads from the cache. Tested on OMAP1510 based Amstrad Delta using linux-omap for-next, commit fb7380d70e041e4b3892f6b19dff7efb609d15a4 (2.6.33-rc3+ dated 2010-01-11). Compile-tested with: omap_perseus2_730_defconfig, omap_generic_1610_defconfig, omap_generic_2420_defconfig, omap_2430sdp_defconfig, omap_3430sdp_defconfig, omap_4430sdp_defconfig with CONFIG_OMAP_MCBSP=y selected. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
255 lines
7.4 KiB
C
255 lines
7.4 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/mcbsp.c
|
|
*
|
|
* Copyright (C) 2008 Instituto Nokia de Tecnologia
|
|
* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* Multichannel mode not supported.
|
|
*/
|
|
#include <linux/module.h>
|
|
#include <linux/init.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/err.h>
|
|
#include <linux/io.h>
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <mach/irqs.h>
|
|
#include <plat/dma.h>
|
|
#include <plat/mux.h>
|
|
#include <plat/cpu.h>
|
|
#include <plat/mcbsp.h>
|
|
|
|
static void omap2_mcbsp2_mux_setup(void)
|
|
{
|
|
omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
|
|
omap_cfg_reg(R14_24XX_MCBSP2_FSX);
|
|
omap_cfg_reg(W15_24XX_MCBSP2_DR);
|
|
omap_cfg_reg(V15_24XX_MCBSP2_DX);
|
|
omap_cfg_reg(V14_24XX_GPIO117);
|
|
/*
|
|
* TODO: Need to add MUX settings for OMAP 2430 SDP
|
|
*/
|
|
}
|
|
|
|
static void omap2_mcbsp_request(unsigned int id)
|
|
{
|
|
if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
|
|
omap2_mcbsp2_mux_setup();
|
|
}
|
|
|
|
static struct omap_mcbsp_ops omap2_mcbsp_ops = {
|
|
.request = omap2_mcbsp_request,
|
|
};
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2420
|
|
static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
|
|
{
|
|
.phys_base = OMAP24XX_MCBSP1_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
|
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP24XX_MCBSP2_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
|
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
};
|
|
#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
|
|
#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
|
|
#else
|
|
#define omap2420_mcbsp_pdata NULL
|
|
#define OMAP2420_MCBSP_PDATA_SZ 0
|
|
#define OMAP2420_MCBSP_REG_NUM 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2430
|
|
static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
|
|
{
|
|
.phys_base = OMAP24XX_MCBSP1_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
|
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP24XX_MCBSP2_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
|
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP2430_MCBSP3_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
|
|
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP2430_MCBSP4_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
|
|
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP2430_MCBSP5_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
|
|
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
};
|
|
#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
|
|
#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
|
|
#else
|
|
#define omap2430_mcbsp_pdata NULL
|
|
#define OMAP2430_MCBSP_PDATA_SZ 0
|
|
#define OMAP2430_MCBSP_REG_NUM 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
|
|
{
|
|
.phys_base = OMAP34XX_MCBSP1_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
|
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
.buffer_size = 0x6F,
|
|
},
|
|
{
|
|
.phys_base = OMAP34XX_MCBSP2_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
|
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
.buffer_size = 0x3FF,
|
|
},
|
|
{
|
|
.phys_base = OMAP34XX_MCBSP3_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
|
|
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
.buffer_size = 0x6F,
|
|
},
|
|
{
|
|
.phys_base = OMAP34XX_MCBSP4_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
|
|
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
.buffer_size = 0x6F,
|
|
},
|
|
{
|
|
.phys_base = OMAP34XX_MCBSP5_BASE,
|
|
.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
|
|
.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
|
|
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
.buffer_size = 0x6F,
|
|
},
|
|
};
|
|
#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
|
|
#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
|
|
#else
|
|
#define omap34xx_mcbsp_pdata NULL
|
|
#define OMAP34XX_MCBSP_PDATA_SZ 0
|
|
#define OMAP34XX_MCBSP_REG_NUM 0
|
|
#endif
|
|
|
|
static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
|
|
{
|
|
.phys_base = OMAP44XX_MCBSP1_BASE,
|
|
.dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
|
|
.dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
|
|
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP44XX_MCBSP2_BASE,
|
|
.dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
|
|
.dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
|
|
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP44XX_MCBSP3_BASE,
|
|
.dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
|
|
.dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
|
|
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
{
|
|
.phys_base = OMAP44XX_MCBSP4_BASE,
|
|
.dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
|
|
.dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
|
|
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
|
|
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
|
|
.ops = &omap2_mcbsp_ops,
|
|
},
|
|
};
|
|
#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
|
|
#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
|
|
|
|
static int __init omap2_mcbsp_init(void)
|
|
{
|
|
if (cpu_is_omap2420()) {
|
|
omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
|
|
omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
|
|
} else if (cpu_is_omap2430()) {
|
|
omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
|
|
omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
|
|
} else if (cpu_is_omap34xx()) {
|
|
omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
|
|
omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
|
|
} else if (cpu_is_omap44xx()) {
|
|
omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
|
|
omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
|
|
}
|
|
|
|
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
|
|
GFP_KERNEL);
|
|
if (!mcbsp_ptr)
|
|
return -ENOMEM;
|
|
|
|
if (cpu_is_omap2420())
|
|
omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
|
|
OMAP2420_MCBSP_PDATA_SZ);
|
|
if (cpu_is_omap2430())
|
|
omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
|
|
OMAP2430_MCBSP_PDATA_SZ);
|
|
if (cpu_is_omap34xx())
|
|
omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
|
|
OMAP34XX_MCBSP_PDATA_SZ);
|
|
if (cpu_is_omap44xx())
|
|
omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
|
|
OMAP44XX_MCBSP_PDATA_SZ);
|
|
|
|
return omap_mcbsp_init();
|
|
}
|
|
arch_initcall(omap2_mcbsp_init);
|