92592c9cca
This patch will add vectored interrupt setups required for MIPS MT modes. irq_cic has been restructured and moved per irq handler to different file. irq_cic has been re wrote to support mips MT modes ( VSMP / SMTC ) [Ralf: fixed some more checkpatch warnings.] Signed-off-by: Anoop P A <anoop.pa@gmail.com> To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org To: dhowells@redhat.com Patchwork: https://patchwork.linux-mips.org/patch/2041/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
179 lines
4.1 KiB
C
179 lines
4.1 KiB
C
/*
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* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
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*
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* This file define the irq handler for MSP PER subsystem interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <msp_cic_int.h>
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#include <msp_regs.h>
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/*
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* Convenience Macro. Should be somewhere generic.
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*/
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#define get_current_vpe() \
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((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
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#ifdef CONFIG_SMP
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/*
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* The PER registers must be protected from concurrent access.
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*/
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static DEFINE_SPINLOCK(per_lock);
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#endif
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/* ensure writes to per are completed */
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static inline void per_wmb(void)
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{
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const volatile void __iomem *per_mem = PER_INT_MSK_REG;
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volatile u32 dummy_read;
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wmb();
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dummy_read = __raw_readl(per_mem);
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dummy_read++;
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}
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static inline void unmask_per_irq(unsigned int irq)
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{
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#ifdef CONFIG_SMP
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unsigned long flags;
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spin_lock_irqsave(&per_lock, flags);
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*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
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spin_unlock_irqrestore(&per_lock, flags);
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#else
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*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
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#endif
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per_wmb();
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}
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static inline void mask_per_irq(unsigned int irq)
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{
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#ifdef CONFIG_SMP
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unsigned long flags;
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spin_lock_irqsave(&per_lock, flags);
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*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
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spin_unlock_irqrestore(&per_lock, flags);
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#else
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*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
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#endif
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per_wmb();
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}
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static inline void msp_per_irq_enable(unsigned int irq)
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{
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unmask_per_irq(irq);
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}
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static inline void msp_per_irq_disable(unsigned int irq)
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{
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mask_per_irq(irq);
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}
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static unsigned int msp_per_irq_startup(unsigned int irq)
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{
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msp_per_irq_enable(irq);
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return 0;
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}
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#define msp_per_irq_shutdown msp_per_irq_disable
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static inline void msp_per_irq_ack(unsigned int irq)
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{
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mask_per_irq(irq);
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/*
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* In the PER interrupt controller, only bits 11 and 10
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* are write-to-clear, (SPI TX complete, SPI RX complete).
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* It does nothing for any others.
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*/
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*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
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/* Re-enable the CIC cascaded interrupt and return */
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irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC);
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}
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static void msp_per_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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unmask_per_irq(irq);
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}
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#ifdef CONFIG_SMP
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static inline int msp_per_irq_set_affinity(unsigned int irq,
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const struct cpumask *affinity)
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{
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unsigned long flags;
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/*
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* Calls to ack, end, startup, enable are spinlocked in setup_irq and
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* __do_IRQ.Callers of this function do not spinlock,so we need to
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* do so ourselves.
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*/
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raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
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msp_per_irq_enable(irq);
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raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
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return 0;
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}
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#endif
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static struct irq_chip msp_per_irq_controller = {
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.name = "MSP_PER",
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.startup = msp_per_irq_startup,
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.shutdown = msp_per_irq_shutdown,
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.enable = msp_per_irq_enable,
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.disable = msp_per_irq_disable,
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#ifdef CONFIG_SMP
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.set_affinity = msp_per_irq_set_affinity,
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#endif
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.ack = msp_per_irq_ack,
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.end = msp_per_irq_end,
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};
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void __init msp_per_irq_init(void)
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{
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int i;
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/* Mask/clear interrupts. */
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*PER_INT_MSK_REG = 0x00000000;
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*PER_INT_STS_REG = 0xFFFFFFFF;
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/* initialize all the IRQ descriptors */
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for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &msp_per_irq_controller;
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#ifdef CONFIG_MIPS_MT_SMTC
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irq_hwmask[i] = C_IRQ4;
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#endif
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}
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}
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void msp_per_irq_dispatch(void)
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{
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u32 per_mask = *PER_INT_MSK_REG;
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u32 per_status = *PER_INT_STS_REG;
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u32 pending;
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pending = per_status & per_mask;
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if (pending) {
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do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1);
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} else {
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spurious_interrupt();
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/* Re-enable the CIC cascaded interrupt and return */
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irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC);
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}
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}
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