256 lines
6.6 KiB
C
256 lines
6.6 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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struct nv50_mpeg_engine {
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struct nouveau_exec_engine base;
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};
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static inline u32
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CTX_PTR(struct drm_device *dev, u32 offset)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->chipset == 0x50)
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offset += 0x0260;
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else
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offset += 0x0060;
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return offset;
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}
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static int
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nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_gpuobj *ctx = NULL;
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int ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ret = nouveau_gpuobj_new(dev, chan, 128 * 4, 0, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ctx);
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if (ret)
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return ret;
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nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
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nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
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nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
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nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
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nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
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nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
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nv_wo32(ctx, 0x70, 0x00801ec1);
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nv_wo32(ctx, 0x7c, 0x0000037c);
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dev_priv->engine.instmem.flush(dev);
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chan->engctx[engine] = ctx;
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return 0;
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}
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static void
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nv50_mpeg_context_del(struct nouveau_channel *chan, int engine)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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unsigned long flags;
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u32 inst, i;
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if (!chan->ramin)
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return;
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inst = chan->ramin->vinst >> 12;
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inst |= 0x80000000;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
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if (nv_rd32(dev, 0x00b318) == inst)
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nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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for (i = 0x00; i <= 0x14; i += 4)
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nv_wo32(chan->ramin, CTX_PTR(dev, i), 0x00000000);
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nouveau_gpuobj_ref(NULL, &ctx);
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chan->engctx[engine] = NULL;
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}
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static int
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nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
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if (ret)
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return ret;
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obj->engine = 2;
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obj->class = class;
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nv_wo32(obj, 0x00, class);
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nv_wo32(obj, 0x04, 0x00000000);
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nv_wo32(obj, 0x08, 0x00000000);
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nv_wo32(obj, 0x0c, 0x00000000);
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dev_priv->engine.instmem.flush(dev);
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ret = nouveau_ramht_insert(chan, handle, obj);
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nouveau_gpuobj_ref(NULL, &obj);
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return ret;
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}
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static void
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nv50_mpeg_tlb_flush(struct drm_device *dev, int engine)
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{
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nv50_vm_flush_engine(dev, 0x08);
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}
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static int
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nv50_mpeg_init(struct drm_device *dev, int engine)
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{
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nv_wr32(dev, 0x00b32c, 0x00000000);
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nv_wr32(dev, 0x00b314, 0x00000100);
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nv_wr32(dev, 0x00b0e0, 0x0000001a);
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nv_wr32(dev, 0x00b220, 0x00000044);
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nv_wr32(dev, 0x00b300, 0x00801ec1);
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nv_wr32(dev, 0x00b390, 0x00000000);
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nv_wr32(dev, 0x00b394, 0x00000000);
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nv_wr32(dev, 0x00b398, 0x00000000);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
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nv_wr32(dev, 0x00b100, 0xffffffff);
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nv_wr32(dev, 0x00b140, 0xffffffff);
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if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
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return -EBUSY;
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}
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return 0;
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}
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static int
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nv50_mpeg_fini(struct drm_device *dev, int engine)
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{
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/*XXX: context save for s/r */
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
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nv_wr32(dev, 0x00b140, 0x00000000);
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return 0;
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}
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static void
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nv50_mpeg_isr(struct drm_device *dev)
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{
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u32 stat = nv_rd32(dev, 0x00b100);
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u32 type = nv_rd32(dev, 0x00b230);
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u32 mthd = nv_rd32(dev, 0x00b234);
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u32 data = nv_rd32(dev, 0x00b238);
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u32 show = stat;
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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if (type == 0x00000020 && mthd == 0x0000) {
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nv_wr32(dev, 0x00b308, 0x00000100);
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show &= ~0x01000000;
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}
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}
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if (show && nouveau_ratelimit()) {
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NV_INFO(dev, "PMPEG - 0x%08x 0x%08x 0x%08x 0x%08x\n",
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stat, type, mthd, data);
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}
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nv_wr32(dev, 0x00b100, stat);
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nv_wr32(dev, 0x00b230, 0x00000001);
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nv50_fb_vm_trap(dev, 1);
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}
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static void
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nv50_vpe_isr(struct drm_device *dev)
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{
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if (nv_rd32(dev, 0x00b100))
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nv50_mpeg_isr(dev);
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if (nv_rd32(dev, 0x00b800)) {
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u32 stat = nv_rd32(dev, 0x00b800);
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NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
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nv_wr32(dev, 0xb800, stat);
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}
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}
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static void
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nv50_mpeg_destroy(struct drm_device *dev, int engine)
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{
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struct nv50_mpeg_engine *pmpeg = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 0);
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NVOBJ_ENGINE_DEL(dev, MPEG);
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kfree(pmpeg);
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}
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int
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nv50_mpeg_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_mpeg_engine *pmpeg;
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pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
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if (!pmpeg)
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return -ENOMEM;
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pmpeg->base.destroy = nv50_mpeg_destroy;
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pmpeg->base.init = nv50_mpeg_init;
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pmpeg->base.fini = nv50_mpeg_fini;
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pmpeg->base.context_new = nv50_mpeg_context_new;
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pmpeg->base.context_del = nv50_mpeg_context_del;
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pmpeg->base.object_new = nv50_mpeg_object_new;
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pmpeg->base.tlb_flush = nv50_mpeg_tlb_flush;
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if (dev_priv->chipset == 0x50) {
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nouveau_irq_register(dev, 0, nv50_vpe_isr);
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NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
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NVOBJ_CLASS(dev, 0x3174, MPEG);
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#if 0
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NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
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NVOBJ_CLASS(dev, 0x4075, ME);
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#endif
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} else {
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nouveau_irq_register(dev, 0, nv50_mpeg_isr);
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NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
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NVOBJ_CLASS(dev, 0x8274, MPEG);
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}
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return 0;
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}
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