af7837c78d
- Add support for B4 board in board file b4_qds.c,
It is common for B4860, B4420 and B4220QDS as they share same QDS board
- Add B4QDS support in Kconfig and Makefile
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor,
with following major features:
- Four dual-threaded e6500 Power Architecture processors
organized in one cluster-each core runs up to 1.8 GHz
- Two DDR3/3L controllers for high-speed memory interface each
runs at up to 1866.67 MHz
- CoreNet fabric that fully supports coherency using MESI protocol
between the e6500 cores, SC3900 FVP cores, memories and
external interfaces.
- Data Path Acceleration Architecture having FMAN, QMan, BMan,
SEC 5.3 and RMAN
- Large internal cache memory with snooping and stashing capabilities
- Sixteen 10-GHz SerDes lanes that serve:
- Two SRIO interfaces. Each supports up to 4 lanes and
a total of up to 8 lanes
- Up to 8-lanes Common Public Radio Interface (CPRI) controller
for glue-less antenna connection
- Two 10-Gbit Ethernet controllers (10GEC)
- Six 1G/2.5-Gbit Ethernet controllers for network communications
- PCI Express controller
- Debug (Aurora)
- Various system peripherals
B4420 and B4220 have some differences in comparison to B4860 with fewer
core/clusters(both SC3900 and e6500), fewer DDR controllers,
fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies.
Key differences between B4860 and B4420:
B4420 has:
- Fewer e6500 cores:
1 cluster with 2 e6500 cores
- Fewer SC3900 cores/clusters:
1 cluster with 2 SC3900 cores per cluster
- Single DDRC @ 1.6GHz
- 2 X 4 lane serdes
- 3 SGMII interfaces
- no sRIO
- no 10G
Key differences between B4860 and B4220:
B4220 has:
- Fewer e6500 cores:
1 cluster with 1 e6500 core
- Fewer SC3900 cores/clusters:
1 cluster with 2 SC3900 cores per cluster
- Single DDRC @ 1.33GHz
- 2 X 2 lane serdes
- 2 SGMII interfaces
- no sRIO
- no 10G
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/*
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* B4 QDS Setup
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* Should apply for QDS platform of B4860 and it's personalities.
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* viz B4860/B4420/B4220QDS
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/phy.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/ehv_pic.h>
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#include "corenet_ds.h"
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init b4_qds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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#ifdef CONFIG_SMP
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extern struct smp_ops_t smp_85xx_ops;
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#endif
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if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
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(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
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(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
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return 1;
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/* Check if we're running under the Freescale hypervisor */
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if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
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(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
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(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
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ppc_md.init_IRQ = ehv_pic_init;
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ppc_md.get_irq = ehv_pic_get_irq;
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ppc_md.restart = fsl_hv_restart;
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ppc_md.power_off = fsl_hv_halt;
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ppc_md.halt = fsl_hv_halt;
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#ifdef CONFIG_SMP
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/*
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* Disable the timebase sync operations because we can't write
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* to the timebase registers under the hypervisor.
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*/
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smp_85xx_ops.give_timebase = NULL;
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smp_85xx_ops.take_timebase = NULL;
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#endif
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return 1;
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}
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return 0;
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}
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define_machine(b4_qds) {
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.name = "B4 QDS",
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.probe = b4_qds_probe,
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.setup_arch = corenet_ds_setup_arch,
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.init_IRQ = corenet_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
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#ifdef CONFIG_PPC64
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.get_irq = mpic_get_irq,
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#else
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.get_irq = mpic_get_coreint_irq,
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#endif
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PPC64
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.power_save = book3e_idle,
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#else
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.power_save = e500_idle,
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#endif
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};
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machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
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#ifdef CONFIG_SWIOTLB
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machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
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#endif
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