0ef0e6ca42
This makes the microdev code a bit more readable, and moves the setup for the SuperIO out on its own. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
160 lines
6.3 KiB
C
160 lines
6.3 KiB
C
/*
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*
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* Setup for the SMSC FDC37C93xAPM
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*
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* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
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* Copyright (C) 2003, 2004 SuperH, Inc.
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* Copyright (C) 2004, 2005 Paul Mundt
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*
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* SuperH SH4-202 MicroDev board support.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach/microdev.h>
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#define SMSC_CONFIG_PORT_ADDR (0x3F0)
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#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
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#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
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#define SMSC_ENTER_CONFIG_KEY 0x55
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#define SMSC_EXIT_CONFIG_KEY 0xaa
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#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
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#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
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#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
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#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
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#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
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#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
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#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
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#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
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#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
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#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
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#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
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#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
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#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
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#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
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#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
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#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
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#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
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#define SMSC_READ_INDEXED(index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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inb(SMSC_DATA_PORT_ADDR); })
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#define SMSC_WRITE_INDEXED(val, index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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outb((val), SMSC_DATA_PORT_ADDR); })
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#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
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#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
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#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
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#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
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#define SERIAL1_PRIMARY_BASE 0x03f8
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#define SERIAL2_PRIMARY_BASE 0x02f8
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#define MSB(x) ( (x) >> 8 )
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#define LSB(x) ( (x) & 0xff )
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/* General-Purpose base address on CPU-board FPGA */
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#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
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static int __init smsc_superio_setup(void)
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{
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unsigned char devid, devrev;
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/* Initially the chip is in run state */
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/* Put it into configuration state */
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outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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/* Read device ID info */
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devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
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devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
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if ((devid == 0x30) && (devrev == 0x01))
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printk("SMSC FDC37C93xAPM SuperIO device detected\n");
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else
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return -ENODEV;
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/* Select the keyboard device */
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SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
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/* Select the Serial #1 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
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/* Select the Serial #2 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#1 device */
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SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
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/* select the interrupt */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#2 device */
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SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
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/* select the interrupt */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
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/* Select the configuration registers */
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SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
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/* enable the appropriate GPIO pins for IDE functionality:
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* bit[0] In/Out 1==input; 0==output
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* bit[1] Polarity 1==invert; 0==no invert
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* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
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* bit[3:4] Function Select 00==original; 01==Alternate Function #1
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*/
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SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
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SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
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SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
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SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
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SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
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/* Exit the configuration state */
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outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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return 0;
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}
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device_initcall(smsc_superio_setup);
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