54293ec307
Here we define the addresses and bit-fields of the Configuration and
Status Registers (CSRs) for some of the hardware functional units on
the OCTEON SOC.
Definitions are needed for:
CIU -- Central Interrupt Unit.
GPIO -- General Purpose Input Output.
IOB -- Input / Output {Busing,Bridge}.
IPD -- Input Packet Data unit.
L2C -- Level-2 Cache controller.
L2D -- Level-2 Data cache.
L2T -- Level-2 cache Tag.
LED -- Light Emitting Diode controller.
MIO -- Miscellaneous Input / Output.
POW -- Packet Order / Work unit.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1616 lines
38 KiB
C
1616 lines
38 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_CIU_DEFS_H__
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#define __CVMX_CIU_DEFS_H__
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#define CVMX_CIU_BIST \
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CVMX_ADD_IO_SEG(0x0001070000000730ull)
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#define CVMX_CIU_DINT \
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CVMX_ADD_IO_SEG(0x0001070000000720ull)
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#define CVMX_CIU_FUSE \
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CVMX_ADD_IO_SEG(0x0001070000000728ull)
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#define CVMX_CIU_GSTOP \
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CVMX_ADD_IO_SEG(0x0001070000000710ull)
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#define CVMX_CIU_INTX_EN0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN0_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN0_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN4_0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_SUM0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
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#define CVMX_CIU_INTX_SUM4(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
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#define CVMX_CIU_INT_SUM1 \
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CVMX_ADD_IO_SEG(0x0001070000000108ull)
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#define CVMX_CIU_MBOX_CLRX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
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#define CVMX_CIU_MBOX_SETX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
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#define CVMX_CIU_NMI \
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CVMX_ADD_IO_SEG(0x0001070000000718ull)
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#define CVMX_CIU_PCI_INTA \
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CVMX_ADD_IO_SEG(0x0001070000000750ull)
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#define CVMX_CIU_PP_DBG \
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CVMX_ADD_IO_SEG(0x0001070000000708ull)
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#define CVMX_CIU_PP_POKEX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
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#define CVMX_CIU_PP_RST \
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CVMX_ADD_IO_SEG(0x0001070000000700ull)
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#define CVMX_CIU_QLM_DCOK \
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CVMX_ADD_IO_SEG(0x0001070000000760ull)
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#define CVMX_CIU_QLM_JTGC \
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CVMX_ADD_IO_SEG(0x0001070000000768ull)
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#define CVMX_CIU_QLM_JTGD \
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CVMX_ADD_IO_SEG(0x0001070000000770ull)
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#define CVMX_CIU_SOFT_BIST \
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CVMX_ADD_IO_SEG(0x0001070000000738ull)
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#define CVMX_CIU_SOFT_PRST \
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CVMX_ADD_IO_SEG(0x0001070000000748ull)
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#define CVMX_CIU_SOFT_PRST1 \
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CVMX_ADD_IO_SEG(0x0001070000000758ull)
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#define CVMX_CIU_SOFT_RST \
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CVMX_ADD_IO_SEG(0x0001070000000740ull)
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#define CVMX_CIU_TIMX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
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#define CVMX_CIU_WDOGX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
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union cvmx_ciu_bist {
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uint64_t u64;
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struct cvmx_ciu_bist_s {
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uint64_t reserved_4_63:60;
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uint64_t bist:4;
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} s;
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struct cvmx_ciu_bist_s cn30xx;
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struct cvmx_ciu_bist_s cn31xx;
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struct cvmx_ciu_bist_s cn38xx;
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struct cvmx_ciu_bist_s cn38xxp2;
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struct cvmx_ciu_bist_cn50xx {
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uint64_t reserved_2_63:62;
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uint64_t bist:2;
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} cn50xx;
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struct cvmx_ciu_bist_cn52xx {
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uint64_t reserved_3_63:61;
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uint64_t bist:3;
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} cn52xx;
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struct cvmx_ciu_bist_cn52xx cn52xxp1;
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struct cvmx_ciu_bist_s cn56xx;
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struct cvmx_ciu_bist_s cn56xxp1;
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struct cvmx_ciu_bist_s cn58xx;
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struct cvmx_ciu_bist_s cn58xxp1;
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};
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union cvmx_ciu_dint {
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uint64_t u64;
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struct cvmx_ciu_dint_s {
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uint64_t reserved_16_63:48;
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uint64_t dint:16;
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} s;
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struct cvmx_ciu_dint_cn30xx {
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uint64_t reserved_1_63:63;
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uint64_t dint:1;
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} cn30xx;
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struct cvmx_ciu_dint_cn31xx {
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uint64_t reserved_2_63:62;
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uint64_t dint:2;
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} cn31xx;
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struct cvmx_ciu_dint_s cn38xx;
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struct cvmx_ciu_dint_s cn38xxp2;
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struct cvmx_ciu_dint_cn31xx cn50xx;
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struct cvmx_ciu_dint_cn52xx {
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uint64_t reserved_4_63:60;
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uint64_t dint:4;
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} cn52xx;
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struct cvmx_ciu_dint_cn52xx cn52xxp1;
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struct cvmx_ciu_dint_cn56xx {
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uint64_t reserved_12_63:52;
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uint64_t dint:12;
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} cn56xx;
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struct cvmx_ciu_dint_cn56xx cn56xxp1;
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struct cvmx_ciu_dint_s cn58xx;
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struct cvmx_ciu_dint_s cn58xxp1;
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};
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union cvmx_ciu_fuse {
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uint64_t u64;
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struct cvmx_ciu_fuse_s {
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uint64_t reserved_16_63:48;
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uint64_t fuse:16;
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} s;
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struct cvmx_ciu_fuse_cn30xx {
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uint64_t reserved_1_63:63;
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uint64_t fuse:1;
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} cn30xx;
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struct cvmx_ciu_fuse_cn31xx {
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uint64_t reserved_2_63:62;
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uint64_t fuse:2;
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} cn31xx;
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struct cvmx_ciu_fuse_s cn38xx;
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struct cvmx_ciu_fuse_s cn38xxp2;
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struct cvmx_ciu_fuse_cn31xx cn50xx;
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struct cvmx_ciu_fuse_cn52xx {
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uint64_t reserved_4_63:60;
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uint64_t fuse:4;
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} cn52xx;
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struct cvmx_ciu_fuse_cn52xx cn52xxp1;
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struct cvmx_ciu_fuse_cn56xx {
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uint64_t reserved_12_63:52;
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uint64_t fuse:12;
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} cn56xx;
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struct cvmx_ciu_fuse_cn56xx cn56xxp1;
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struct cvmx_ciu_fuse_s cn58xx;
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struct cvmx_ciu_fuse_s cn58xxp1;
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};
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union cvmx_ciu_gstop {
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uint64_t u64;
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struct cvmx_ciu_gstop_s {
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uint64_t reserved_1_63:63;
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uint64_t gstop:1;
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} s;
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struct cvmx_ciu_gstop_s cn30xx;
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struct cvmx_ciu_gstop_s cn31xx;
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struct cvmx_ciu_gstop_s cn38xx;
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struct cvmx_ciu_gstop_s cn38xxp2;
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struct cvmx_ciu_gstop_s cn50xx;
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struct cvmx_ciu_gstop_s cn52xx;
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struct cvmx_ciu_gstop_s cn52xxp1;
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struct cvmx_ciu_gstop_s cn56xx;
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struct cvmx_ciu_gstop_s cn56xxp1;
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struct cvmx_ciu_gstop_s cn58xx;
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struct cvmx_ciu_gstop_s cn58xxp1;
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};
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union cvmx_ciu_intx_en0 {
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uint64_t u64;
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struct cvmx_ciu_intx_en0_s {
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uint64_t bootdma:1;
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uint64_t mii:1;
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uint64_t ipdppthr:1;
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uint64_t powiq:1;
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uint64_t twsi2:1;
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uint64_t mpi:1;
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uint64_t pcm:1;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t key_zero:1;
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uint64_t ipd_drp:1;
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uint64_t gmx_drp:2;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} s;
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struct cvmx_ciu_intx_en0_cn30xx {
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uint64_t reserved_59_63:5;
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uint64_t mpi:1;
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uint64_t pcm:1;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t reserved_51_51:1;
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uint64_t ipd_drp:1;
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uint64_t reserved_49_49:1;
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uint64_t gmx_drp:1;
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uint64_t reserved_47_47:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} cn30xx;
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struct cvmx_ciu_intx_en0_cn31xx {
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uint64_t reserved_59_63:5;
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uint64_t mpi:1;
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uint64_t pcm:1;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t reserved_51_51:1;
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uint64_t ipd_drp:1;
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uint64_t reserved_49_49:1;
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uint64_t gmx_drp:1;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} cn31xx;
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struct cvmx_ciu_intx_en0_cn38xx {
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uint64_t reserved_56_63:8;
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uint64_t timer:4;
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uint64_t key_zero:1;
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uint64_t ipd_drp:1;
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uint64_t gmx_drp:2;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} cn38xx;
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struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
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struct cvmx_ciu_intx_en0_cn30xx cn50xx;
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struct cvmx_ciu_intx_en0_cn52xx {
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uint64_t bootdma:1;
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uint64_t mii:1;
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uint64_t ipdppthr:1;
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uint64_t powiq:1;
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uint64_t twsi2:1;
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uint64_t reserved_57_58:2;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t reserved_51_51:1;
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uint64_t ipd_drp:1;
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uint64_t reserved_49_49:1;
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uint64_t gmx_drp:1;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} cn52xx;
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struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
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struct cvmx_ciu_intx_en0_cn56xx {
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uint64_t bootdma:1;
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uint64_t mii:1;
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uint64_t ipdppthr:1;
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uint64_t powiq:1;
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uint64_t twsi2:1;
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uint64_t reserved_57_58:2;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t key_zero:1;
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uint64_t ipd_drp:1;
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uint64_t gmx_drp:2;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} cn56xx;
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struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
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struct cvmx_ciu_intx_en0_cn38xx cn58xx;
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struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
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};
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union cvmx_ciu_intx_en0_w1c {
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uint64_t u64;
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struct cvmx_ciu_intx_en0_w1c_s {
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uint64_t bootdma:1;
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uint64_t mii:1;
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uint64_t ipdppthr:1;
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uint64_t powiq:1;
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uint64_t twsi2:1;
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uint64_t reserved_57_58:2;
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|
uint64_t usb:1;
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uint64_t timer:4;
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uint64_t key_zero:1;
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uint64_t ipd_drp:1;
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uint64_t gmx_drp:2;
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uint64_t trace:1;
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uint64_t rml:1;
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uint64_t twsi:1;
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uint64_t reserved_44_44:1;
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uint64_t pci_msi:4;
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uint64_t pci_int:4;
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uint64_t uart:2;
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uint64_t mbox:2;
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uint64_t gpio:16;
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uint64_t workq:16;
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} s;
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struct cvmx_ciu_intx_en0_w1c_cn52xx {
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uint64_t bootdma:1;
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uint64_t mii:1;
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uint64_t ipdppthr:1;
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uint64_t powiq:1;
|
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uint64_t twsi2:1;
|
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uint64_t reserved_57_58:2;
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uint64_t usb:1;
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uint64_t timer:4;
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uint64_t reserved_51_51:1;
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uint64_t ipd_drp:1;
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uint64_t reserved_49_49:1;
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uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en0_w1c_s cn56xx;
|
|
struct cvmx_ciu_intx_en0_w1c_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en0_w1s {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en0_w1s_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en0_w1s_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en0_w1s_s cn56xx;
|
|
struct cvmx_ciu_intx_en0_w1s_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en1 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en1_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en1_cn30xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t wdog:1;
|
|
} cn30xx;
|
|
struct cvmx_ciu_intx_en1_cn31xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t wdog:2;
|
|
} cn31xx;
|
|
struct cvmx_ciu_intx_en1_cn38xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn38xx;
|
|
struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
|
|
struct cvmx_ciu_intx_en1_cn31xx cn50xx;
|
|
struct cvmx_ciu_intx_en1_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en1_cn52xxp1 {
|
|
uint64_t reserved_19_63:45;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xxp1;
|
|
struct cvmx_ciu_intx_en1_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_intx_en1_cn38xx cn58xx;
|
|
struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en1_w1c {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en1_w1c_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en1_w1c_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en1_w1c_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en1_w1c_cn58xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en1_w1s {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en1_w1s_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en1_w1s_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en1_w1s_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en1_w1s_cn58xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_0 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_0_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_0_cn50xx {
|
|
uint64_t reserved_59_63:5;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t reserved_47_47:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn50xx;
|
|
struct cvmx_ciu_intx_en4_0_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_intx_en4_0_cn56xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_intx_en4_0_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_0_w1c {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_0_w1c_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
|
|
struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_0_w1s {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_0_w1s_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
|
|
struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t reserved_44_44:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_1 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_1_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_1_cn50xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t wdog:2;
|
|
} cn50xx;
|
|
struct cvmx_ciu_intx_en4_1_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_1_cn52xxp1 {
|
|
uint64_t reserved_19_63:45;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xxp1;
|
|
struct cvmx_ciu_intx_en4_1_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_intx_en4_1_cn58xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn58xx;
|
|
struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_1_w1c {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_1_w1c_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_en4_1_w1s {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_en4_1_w1s_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn58xx;
|
|
};
|
|
|
|
union cvmx_ciu_intx_sum0 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_sum0_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_sum0_cn30xx {
|
|
uint64_t reserved_59_63:5;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t reserved_47_47:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn30xx;
|
|
struct cvmx_ciu_intx_sum0_cn31xx {
|
|
uint64_t reserved_59_63:5;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn31xx;
|
|
struct cvmx_ciu_intx_sum0_cn38xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn38xx;
|
|
struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
|
|
struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
|
|
struct cvmx_ciu_intx_sum0_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_intx_sum0_cn56xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
|
|
struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_intx_sum4 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_intx_sum4_s {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} s;
|
|
struct cvmx_ciu_intx_sum4_cn50xx {
|
|
uint64_t reserved_59_63:5;
|
|
uint64_t mpi:1;
|
|
uint64_t pcm:1;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t reserved_47_47:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn50xx;
|
|
struct cvmx_ciu_intx_sum4_cn52xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t reserved_51_51:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t reserved_49_49:1;
|
|
uint64_t gmx_drp:1;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn52xx;
|
|
struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_intx_sum4_cn56xx {
|
|
uint64_t bootdma:1;
|
|
uint64_t mii:1;
|
|
uint64_t ipdppthr:1;
|
|
uint64_t powiq:1;
|
|
uint64_t twsi2:1;
|
|
uint64_t reserved_57_58:2;
|
|
uint64_t usb:1;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn56xx;
|
|
struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_intx_sum4_cn58xx {
|
|
uint64_t reserved_56_63:8;
|
|
uint64_t timer:4;
|
|
uint64_t key_zero:1;
|
|
uint64_t ipd_drp:1;
|
|
uint64_t gmx_drp:2;
|
|
uint64_t trace:1;
|
|
uint64_t rml:1;
|
|
uint64_t twsi:1;
|
|
uint64_t wdog_sum:1;
|
|
uint64_t pci_msi:4;
|
|
uint64_t pci_int:4;
|
|
uint64_t uart:2;
|
|
uint64_t mbox:2;
|
|
uint64_t gpio:16;
|
|
uint64_t workq:16;
|
|
} cn58xx;
|
|
struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_int_sum1 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_int_sum1_s {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t wdog:16;
|
|
} s;
|
|
struct cvmx_ciu_int_sum1_cn30xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t wdog:1;
|
|
} cn30xx;
|
|
struct cvmx_ciu_int_sum1_cn31xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t wdog:2;
|
|
} cn31xx;
|
|
struct cvmx_ciu_int_sum1_cn38xx {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t wdog:16;
|
|
} cn38xx;
|
|
struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
|
|
struct cvmx_ciu_int_sum1_cn31xx cn50xx;
|
|
struct cvmx_ciu_int_sum1_cn52xx {
|
|
uint64_t reserved_20_63:44;
|
|
uint64_t nand:1;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_int_sum1_cn52xxp1 {
|
|
uint64_t reserved_19_63:45;
|
|
uint64_t mii1:1;
|
|
uint64_t usb1:1;
|
|
uint64_t uart2:1;
|
|
uint64_t reserved_4_15:12;
|
|
uint64_t wdog:4;
|
|
} cn52xxp1;
|
|
struct cvmx_ciu_int_sum1_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t wdog:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_int_sum1_cn38xx cn58xx;
|
|
struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_mbox_clrx {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_mbox_clrx_s {
|
|
uint64_t reserved_32_63:32;
|
|
uint64_t bits:32;
|
|
} s;
|
|
struct cvmx_ciu_mbox_clrx_s cn30xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn31xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn38xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn38xxp2;
|
|
struct cvmx_ciu_mbox_clrx_s cn50xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn52xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn52xxp1;
|
|
struct cvmx_ciu_mbox_clrx_s cn56xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn56xxp1;
|
|
struct cvmx_ciu_mbox_clrx_s cn58xx;
|
|
struct cvmx_ciu_mbox_clrx_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_mbox_setx {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_mbox_setx_s {
|
|
uint64_t reserved_32_63:32;
|
|
uint64_t bits:32;
|
|
} s;
|
|
struct cvmx_ciu_mbox_setx_s cn30xx;
|
|
struct cvmx_ciu_mbox_setx_s cn31xx;
|
|
struct cvmx_ciu_mbox_setx_s cn38xx;
|
|
struct cvmx_ciu_mbox_setx_s cn38xxp2;
|
|
struct cvmx_ciu_mbox_setx_s cn50xx;
|
|
struct cvmx_ciu_mbox_setx_s cn52xx;
|
|
struct cvmx_ciu_mbox_setx_s cn52xxp1;
|
|
struct cvmx_ciu_mbox_setx_s cn56xx;
|
|
struct cvmx_ciu_mbox_setx_s cn56xxp1;
|
|
struct cvmx_ciu_mbox_setx_s cn58xx;
|
|
struct cvmx_ciu_mbox_setx_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_nmi {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_nmi_s {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t nmi:16;
|
|
} s;
|
|
struct cvmx_ciu_nmi_cn30xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t nmi:1;
|
|
} cn30xx;
|
|
struct cvmx_ciu_nmi_cn31xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t nmi:2;
|
|
} cn31xx;
|
|
struct cvmx_ciu_nmi_s cn38xx;
|
|
struct cvmx_ciu_nmi_s cn38xxp2;
|
|
struct cvmx_ciu_nmi_cn31xx cn50xx;
|
|
struct cvmx_ciu_nmi_cn52xx {
|
|
uint64_t reserved_4_63:60;
|
|
uint64_t nmi:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_nmi_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_nmi_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t nmi:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_nmi_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_nmi_s cn58xx;
|
|
struct cvmx_ciu_nmi_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_pci_inta {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_pci_inta_s {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t intr:2;
|
|
} s;
|
|
struct cvmx_ciu_pci_inta_s cn30xx;
|
|
struct cvmx_ciu_pci_inta_s cn31xx;
|
|
struct cvmx_ciu_pci_inta_s cn38xx;
|
|
struct cvmx_ciu_pci_inta_s cn38xxp2;
|
|
struct cvmx_ciu_pci_inta_s cn50xx;
|
|
struct cvmx_ciu_pci_inta_s cn52xx;
|
|
struct cvmx_ciu_pci_inta_s cn52xxp1;
|
|
struct cvmx_ciu_pci_inta_s cn56xx;
|
|
struct cvmx_ciu_pci_inta_s cn56xxp1;
|
|
struct cvmx_ciu_pci_inta_s cn58xx;
|
|
struct cvmx_ciu_pci_inta_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_pp_dbg {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_pp_dbg_s {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t ppdbg:16;
|
|
} s;
|
|
struct cvmx_ciu_pp_dbg_cn30xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t ppdbg:1;
|
|
} cn30xx;
|
|
struct cvmx_ciu_pp_dbg_cn31xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t ppdbg:2;
|
|
} cn31xx;
|
|
struct cvmx_ciu_pp_dbg_s cn38xx;
|
|
struct cvmx_ciu_pp_dbg_s cn38xxp2;
|
|
struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
|
|
struct cvmx_ciu_pp_dbg_cn52xx {
|
|
uint64_t reserved_4_63:60;
|
|
uint64_t ppdbg:4;
|
|
} cn52xx;
|
|
struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_pp_dbg_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t ppdbg:12;
|
|
} cn56xx;
|
|
struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_pp_dbg_s cn58xx;
|
|
struct cvmx_ciu_pp_dbg_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_pp_pokex {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_pp_pokex_s {
|
|
uint64_t reserved_0_63:64;
|
|
} s;
|
|
struct cvmx_ciu_pp_pokex_s cn30xx;
|
|
struct cvmx_ciu_pp_pokex_s cn31xx;
|
|
struct cvmx_ciu_pp_pokex_s cn38xx;
|
|
struct cvmx_ciu_pp_pokex_s cn38xxp2;
|
|
struct cvmx_ciu_pp_pokex_s cn50xx;
|
|
struct cvmx_ciu_pp_pokex_s cn52xx;
|
|
struct cvmx_ciu_pp_pokex_s cn52xxp1;
|
|
struct cvmx_ciu_pp_pokex_s cn56xx;
|
|
struct cvmx_ciu_pp_pokex_s cn56xxp1;
|
|
struct cvmx_ciu_pp_pokex_s cn58xx;
|
|
struct cvmx_ciu_pp_pokex_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_pp_rst {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_pp_rst_s {
|
|
uint64_t reserved_16_63:48;
|
|
uint64_t rst:15;
|
|
uint64_t rst0:1;
|
|
} s;
|
|
struct cvmx_ciu_pp_rst_cn30xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t rst0:1;
|
|
} cn30xx;
|
|
struct cvmx_ciu_pp_rst_cn31xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t rst:1;
|
|
uint64_t rst0:1;
|
|
} cn31xx;
|
|
struct cvmx_ciu_pp_rst_s cn38xx;
|
|
struct cvmx_ciu_pp_rst_s cn38xxp2;
|
|
struct cvmx_ciu_pp_rst_cn31xx cn50xx;
|
|
struct cvmx_ciu_pp_rst_cn52xx {
|
|
uint64_t reserved_4_63:60;
|
|
uint64_t rst:3;
|
|
uint64_t rst0:1;
|
|
} cn52xx;
|
|
struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_pp_rst_cn56xx {
|
|
uint64_t reserved_12_63:52;
|
|
uint64_t rst:11;
|
|
uint64_t rst0:1;
|
|
} cn56xx;
|
|
struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
|
|
struct cvmx_ciu_pp_rst_s cn58xx;
|
|
struct cvmx_ciu_pp_rst_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_qlm_dcok {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_qlm_dcok_s {
|
|
uint64_t reserved_4_63:60;
|
|
uint64_t qlm_dcok:4;
|
|
} s;
|
|
struct cvmx_ciu_qlm_dcok_cn52xx {
|
|
uint64_t reserved_2_63:62;
|
|
uint64_t qlm_dcok:2;
|
|
} cn52xx;
|
|
struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_qlm_dcok_s cn56xx;
|
|
struct cvmx_ciu_qlm_dcok_s cn56xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_qlm_jtgc {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_qlm_jtgc_s {
|
|
uint64_t reserved_11_63:53;
|
|
uint64_t clk_div:3;
|
|
uint64_t reserved_6_7:2;
|
|
uint64_t mux_sel:2;
|
|
uint64_t bypass:4;
|
|
} s;
|
|
struct cvmx_ciu_qlm_jtgc_cn52xx {
|
|
uint64_t reserved_11_63:53;
|
|
uint64_t clk_div:3;
|
|
uint64_t reserved_5_7:3;
|
|
uint64_t mux_sel:1;
|
|
uint64_t reserved_2_3:2;
|
|
uint64_t bypass:2;
|
|
} cn52xx;
|
|
struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_qlm_jtgc_s cn56xx;
|
|
struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_qlm_jtgd {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_qlm_jtgd_s {
|
|
uint64_t capture:1;
|
|
uint64_t shift:1;
|
|
uint64_t update:1;
|
|
uint64_t reserved_44_60:17;
|
|
uint64_t select:4;
|
|
uint64_t reserved_37_39:3;
|
|
uint64_t shft_cnt:5;
|
|
uint64_t shft_reg:32;
|
|
} s;
|
|
struct cvmx_ciu_qlm_jtgd_cn52xx {
|
|
uint64_t capture:1;
|
|
uint64_t shift:1;
|
|
uint64_t update:1;
|
|
uint64_t reserved_42_60:19;
|
|
uint64_t select:2;
|
|
uint64_t reserved_37_39:3;
|
|
uint64_t shft_cnt:5;
|
|
uint64_t shft_reg:32;
|
|
} cn52xx;
|
|
struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_qlm_jtgd_s cn56xx;
|
|
struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
|
|
uint64_t capture:1;
|
|
uint64_t shift:1;
|
|
uint64_t update:1;
|
|
uint64_t reserved_37_60:24;
|
|
uint64_t shft_cnt:5;
|
|
uint64_t shft_reg:32;
|
|
} cn56xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_soft_bist {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_soft_bist_s {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t soft_bist:1;
|
|
} s;
|
|
struct cvmx_ciu_soft_bist_s cn30xx;
|
|
struct cvmx_ciu_soft_bist_s cn31xx;
|
|
struct cvmx_ciu_soft_bist_s cn38xx;
|
|
struct cvmx_ciu_soft_bist_s cn38xxp2;
|
|
struct cvmx_ciu_soft_bist_s cn50xx;
|
|
struct cvmx_ciu_soft_bist_s cn52xx;
|
|
struct cvmx_ciu_soft_bist_s cn52xxp1;
|
|
struct cvmx_ciu_soft_bist_s cn56xx;
|
|
struct cvmx_ciu_soft_bist_s cn56xxp1;
|
|
struct cvmx_ciu_soft_bist_s cn58xx;
|
|
struct cvmx_ciu_soft_bist_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_soft_prst {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_soft_prst_s {
|
|
uint64_t reserved_3_63:61;
|
|
uint64_t host64:1;
|
|
uint64_t npi:1;
|
|
uint64_t soft_prst:1;
|
|
} s;
|
|
struct cvmx_ciu_soft_prst_s cn30xx;
|
|
struct cvmx_ciu_soft_prst_s cn31xx;
|
|
struct cvmx_ciu_soft_prst_s cn38xx;
|
|
struct cvmx_ciu_soft_prst_s cn38xxp2;
|
|
struct cvmx_ciu_soft_prst_s cn50xx;
|
|
struct cvmx_ciu_soft_prst_cn52xx {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t soft_prst:1;
|
|
} cn52xx;
|
|
struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
|
|
struct cvmx_ciu_soft_prst_cn52xx cn56xx;
|
|
struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
|
|
struct cvmx_ciu_soft_prst_s cn58xx;
|
|
struct cvmx_ciu_soft_prst_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_soft_prst1 {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_soft_prst1_s {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t soft_prst:1;
|
|
} s;
|
|
struct cvmx_ciu_soft_prst1_s cn52xx;
|
|
struct cvmx_ciu_soft_prst1_s cn52xxp1;
|
|
struct cvmx_ciu_soft_prst1_s cn56xx;
|
|
struct cvmx_ciu_soft_prst1_s cn56xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_soft_rst {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_soft_rst_s {
|
|
uint64_t reserved_1_63:63;
|
|
uint64_t soft_rst:1;
|
|
} s;
|
|
struct cvmx_ciu_soft_rst_s cn30xx;
|
|
struct cvmx_ciu_soft_rst_s cn31xx;
|
|
struct cvmx_ciu_soft_rst_s cn38xx;
|
|
struct cvmx_ciu_soft_rst_s cn38xxp2;
|
|
struct cvmx_ciu_soft_rst_s cn50xx;
|
|
struct cvmx_ciu_soft_rst_s cn52xx;
|
|
struct cvmx_ciu_soft_rst_s cn52xxp1;
|
|
struct cvmx_ciu_soft_rst_s cn56xx;
|
|
struct cvmx_ciu_soft_rst_s cn56xxp1;
|
|
struct cvmx_ciu_soft_rst_s cn58xx;
|
|
struct cvmx_ciu_soft_rst_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_timx {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_timx_s {
|
|
uint64_t reserved_37_63:27;
|
|
uint64_t one_shot:1;
|
|
uint64_t len:36;
|
|
} s;
|
|
struct cvmx_ciu_timx_s cn30xx;
|
|
struct cvmx_ciu_timx_s cn31xx;
|
|
struct cvmx_ciu_timx_s cn38xx;
|
|
struct cvmx_ciu_timx_s cn38xxp2;
|
|
struct cvmx_ciu_timx_s cn50xx;
|
|
struct cvmx_ciu_timx_s cn52xx;
|
|
struct cvmx_ciu_timx_s cn52xxp1;
|
|
struct cvmx_ciu_timx_s cn56xx;
|
|
struct cvmx_ciu_timx_s cn56xxp1;
|
|
struct cvmx_ciu_timx_s cn58xx;
|
|
struct cvmx_ciu_timx_s cn58xxp1;
|
|
};
|
|
|
|
union cvmx_ciu_wdogx {
|
|
uint64_t u64;
|
|
struct cvmx_ciu_wdogx_s {
|
|
uint64_t reserved_46_63:18;
|
|
uint64_t gstopen:1;
|
|
uint64_t dstop:1;
|
|
uint64_t cnt:24;
|
|
uint64_t len:16;
|
|
uint64_t state:2;
|
|
uint64_t mode:2;
|
|
} s;
|
|
struct cvmx_ciu_wdogx_s cn30xx;
|
|
struct cvmx_ciu_wdogx_s cn31xx;
|
|
struct cvmx_ciu_wdogx_s cn38xx;
|
|
struct cvmx_ciu_wdogx_s cn38xxp2;
|
|
struct cvmx_ciu_wdogx_s cn50xx;
|
|
struct cvmx_ciu_wdogx_s cn52xx;
|
|
struct cvmx_ciu_wdogx_s cn52xxp1;
|
|
struct cvmx_ciu_wdogx_s cn56xx;
|
|
struct cvmx_ciu_wdogx_s cn56xxp1;
|
|
struct cvmx_ciu_wdogx_s cn58xx;
|
|
struct cvmx_ciu_wdogx_s cn58xxp1;
|
|
};
|
|
|
|
#endif
|