a072738e04
The netburst PMU is way different from the "architectural perfomance monitoring" specification that current CPUs use. P4 uses a tuple of ESCR+CCCR+COUNTER MSR registers to handle perfomance monitoring events. A few implementational details: 1) We need a separate x86_pmu::hw_config helper in struct x86_pmu since register bit-fields are quite different from P6, Core and later cpu series. 2) For the same reason is a x86_pmu::schedule_events helper introduced. 3) hw_perf_event::config consists of packed ESCR+CCCR values. It's allowed since in reality both registers only use a half of their size. Of course before making a real write into a particular MSR we need to unpack the value and extend it to a proper size. 4) The tuple of packed ESCR+CCCR in hw_perf_event::config doesn't describe the memory address of ESCR MSR register so that we need to keep a mapping between these tuples used and available ESCR (various P4 events may use same ESCRs but not simultaneously), for this sake every active event has a per-cpu map of hw_perf_event::idx <--> ESCR addresses. 5) Since hw_perf_event::idx is an offset to counter/control register we need to lift X86_PMC_MAX_GENERIC up, otherwise kernel strips it down to 8 registers and event armed may never be turned off (ie the bit in active_mask is set but the loop never reaches this index to check), thanks to Peter Zijlstra Restrictions: - No cascaded counters support (do we ever need them?) - No dependent events support (so PERF_COUNT_HW_INSTRUCTIONS doesn't work for now) - There are events with same counters which can't work simultaneously (need to use intersected ones due to broken counter 1) - No PERF_COUNT_HW_CACHE_ events yet Todo: - Implement dependent events - Need proper hashing for event opcodes (no linear search, good for debugging stage but not in real loads) - Some events counted during a clock cycle -- need to set threshold for them and count every clock cycle just to get summary statistics (ie to behave the same way as other PMUs do) - Need to swicth to use event_constraints - To support RAW events we need to encode a global list of P4 events into p4_templates - Cache events need to be added Event support status matrix: Event status ----------------------------- cycles works cache-references works cache-misses works branch-misses works bus-cycles partially (does not work on 64bit cpu with HT enabled) instruction doesnt work (needs dependent event [mop tagging]) branches doesnt work Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Stephane Eranian <eranian@google.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <20100311165439.GB5129@lenovo> Signed-off-by: Ingo Molnar <mingo@elte.hu>
163 lines
4.3 KiB
C
163 lines
4.3 KiB
C
#ifndef _ASM_X86_PERF_EVENT_H
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#define _ASM_X86_PERF_EVENT_H
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/*
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* Performance event hw details:
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*/
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#define X86_PMC_MAX_GENERIC 32
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#define X86_PMC_MAX_FIXED 3
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#define X86_PMC_IDX_GENERIC 0
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#define X86_PMC_IDX_FIXED 32
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#define X86_PMC_IDX_MAX 64
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL_ENABLE (1 << 22)
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#define ARCH_PERFMON_EVENTSEL_ANY (1 << 21)
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#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
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#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
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#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
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/*
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* Includes eventsel and unit mask as well:
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*/
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#define INTEL_ARCH_EVTSEL_MASK 0x000000FFULL
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#define INTEL_ARCH_UNIT_MASK 0x0000FF00ULL
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#define INTEL_ARCH_EDGE_MASK 0x00040000ULL
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#define INTEL_ARCH_INV_MASK 0x00800000ULL
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#define INTEL_ARCH_CNT_MASK 0xFF000000ULL
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#define INTEL_ARCH_EVENT_MASK (INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)
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/*
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* filter mask to validate fixed counter events.
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* the following filters disqualify for fixed counters:
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* - inv
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* - edge
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* - cnt-mask
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* The other filters are supported by fixed counters.
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* The any-thread option is supported starting with v3.
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*/
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#define INTEL_ARCH_FIXED_MASK \
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(INTEL_ARCH_CNT_MASK| \
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INTEL_ARCH_INV_MASK| \
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INTEL_ARCH_EDGE_MASK|\
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INTEL_ARCH_UNIT_MASK|\
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INTEL_ARCH_EVENT_MASK)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
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(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
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#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
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/*
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* Intel "Architectural Performance Monitoring" CPUID
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* detection/enumeration details:
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*/
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union cpuid10_eax {
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struct {
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unsigned int version_id:8;
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unsigned int num_events:8;
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unsigned int bit_width:8;
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unsigned int mask_length:8;
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} split;
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unsigned int full;
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};
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union cpuid10_edx {
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struct {
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unsigned int num_events_fixed:4;
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unsigned int reserved:28;
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} split;
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unsigned int full;
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};
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/*
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* Fixed-purpose performance events:
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*/
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/*
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* All 3 fixed-mode PMCs are configured via this single MSR:
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*/
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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/*
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* The counts are available in three separate MSRs:
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*/
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/* Instr_Retired.Any: */
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
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/* CPU_CLK_Unhalted.Core: */
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
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/* CPU_CLK_Unhalted.Ref: */
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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*
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* We choose a value in the middle of the fixed event range, since lower
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* values are used by actual fixed events and higher values are used
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
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*/
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#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT 0xFFFF0000ULL
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* IbsOpCtl bits */
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_OP_MAX_CNT 0x0000FFFFULL
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#ifdef CONFIG_PERF_EVENTS
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extern void init_hw_perf_events(void);
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extern void perf_events_lapic_init(void);
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#define PERF_EVENT_INDEX_OFFSET 0
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/*
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* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
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* This flag is otherwise unused and ABI specified to be 0, so nobody should
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* care what we do with it.
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*/
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#define PERF_EFLAGS_EXACT (1UL << 3)
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#define perf_misc_flags(regs) \
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({ int misc = 0; \
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if (user_mode(regs)) \
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misc |= PERF_RECORD_MISC_USER; \
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else \
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misc |= PERF_RECORD_MISC_KERNEL; \
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if (regs->flags & PERF_EFLAGS_EXACT) \
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misc |= PERF_RECORD_MISC_EXACT; \
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misc; })
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#define perf_instruction_pointer(regs) ((regs)->ip)
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#else
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static inline void init_hw_perf_events(void) { }
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static inline void perf_events_lapic_init(void) { }
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#endif
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#endif /* _ASM_X86_PERF_EVENT_H */
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