548153663b
In all current use cases, "chipdata" is used to store an iomem address. Mark it with __iomem, and rename it to 'base'. Leave the accessor macros alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
329 lines
7.9 KiB
C
329 lines
7.9 KiB
C
/*
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* linux/arch/arm/mach-at91rm9200/gpio.c
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*
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* Copyright (C) 2005 HP Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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static const u32 pio_controller_offset[4] = {
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AT91_PIOA,
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AT91_PIOB,
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AT91_PIOC,
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AT91_PIOD,
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};
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static inline void __iomem *pin_to_controller(unsigned pin)
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{
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void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
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pin -= PIN_BASE;
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pin /= 32;
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if (likely(pin < BGA_GPIO_BANKS))
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return sys_base + pio_controller_offset[pin];
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return NULL;
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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pin -= PIN_BASE;
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return 1 << (pin % 32);
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}
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/*--------------------------------------------------------------------------*/
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/* Not all hardware capabilities are exposed through these calls; they
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* only encapsulate the most common features and modes. (So if you
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* want to change signals in groups, do it directly.)
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*
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* Bootloaders will usually handle some of the pin multiplexing setup.
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* The intent is certainly that by the time Linux is fully booted, all
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* pins should have been fully initialized. These setup calls should
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* only be used by board setup routines, or possibly in driver probe().
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*
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* For bootloaders doing all that setup, these calls could be inlined
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* as NOPs so Linux won't duplicate any setup code
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*/
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ASR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_A_periph);
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_BSR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_B_periph);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ODR);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int __init_or_module at91_set_gpio_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_deglitch);
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_multi_drive);
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/*--------------------------------------------------------------------------*/
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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int at91_set_gpio_value(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_value);
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int at91_get_gpio_value(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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if (!pio)
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return -EINVAL;
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pdsr = __raw_readl(pio + PIO_PDSR);
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return (pdsr & mask) != 0;
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}
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EXPORT_SYMBOL(at91_get_gpio_value);
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/*--------------------------------------------------------------------------*/
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/* Several AIC controller irqs are dispatched through this GPIO handler.
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* To use any AT91_PIN_* as an externally triggered IRQ, first call
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* at91_set_gpio_input() then maybe enable its glitch filter.
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* Then just request_irq() with the pin ID; it works like any ARM IRQ
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* handler, though it always triggers on rising and falling edges.
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*
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* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
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* configuring them with at91_set_a_periph() or at91_set_b_periph().
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* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
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*/
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static void gpio_irq_mask(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (pio)
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__raw_writel(mask, pio + PIO_IDR);
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}
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static void gpio_irq_unmask(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (pio)
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__raw_writel(mask, pio + PIO_IER);
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}
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static int gpio_irq_type(unsigned pin, unsigned type)
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{
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return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
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}
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static struct irqchip gpio_irqchip = {
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.mask = gpio_irq_mask,
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.unmask = gpio_irq_unmask,
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.set_type = gpio_irq_type,
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};
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static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
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{
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unsigned pin;
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struct irqdesc *gpio;
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void __iomem *pio;
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u32 isr;
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pio = desc->base;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->chip->ack(irq);
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for (;;) {
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isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
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if (!isr)
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break;
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pin = (unsigned) desc->data;
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gpio = &irq_desc[pin];
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while (isr) {
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if (isr & 1) {
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if (unlikely(gpio->disable_depth)) {
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/*
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* The core ARM interrupt handler lazily disables IRQs so
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* another IRQ must be generated before it actually gets
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* here to be disabled on the GPIO controller.
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*/
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gpio_irq_mask(pin);
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}
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else
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gpio->handle(pin, gpio, regs);
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}
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pin++;
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gpio++;
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isr >>= 1;
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}
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}
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desc->chip->unmask(irq);
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/* now it may re-trigger */
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}
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/* call this from board-specific init_irq */
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void __init at91_gpio_irq_setup(unsigned banks)
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{
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unsigned pioc, pin, id;
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if (banks > 4)
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banks = 4;
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for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
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pioc < banks;
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pioc++, id++) {
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void __iomem *controller;
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unsigned i;
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controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
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__raw_writel(~0, controller + PIO_IDR);
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set_irq_data(id, (void *) pin);
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set_irq_chipdata(id, controller);
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for (i = 0; i < 32; i++, pin++) {
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set_irq_chip(pin, &gpio_irqchip);
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set_irq_handler(pin, do_simple_IRQ);
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set_irq_flags(pin, IRQF_VALID);
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}
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set_irq_chained_handler(id, gpio_irq_handler);
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/* enable the PIO peripheral clock */
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at91_sys_write(AT91_PMC_PCER, 1 << id);
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}
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pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
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}
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