3ec18cd8b8
This patch enables perf_events support for Intel Cedarview Atom (model 54) processors. Support includes PEBS and LBR. Tested on my Atom N2600 netbook. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20120820092421.GA11284@quad Signed-off-by: Ingo Molnar <mingo@kernel.org>
705 lines
16 KiB
C
705 lines
16 KiB
C
#include <linux/perf_event.h>
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#include <linux/types.h>
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#include <asm/perf_event.h>
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#include <asm/msr.h>
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#include <asm/insn.h>
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#include "perf_event.h"
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enum {
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LBR_FORMAT_32 = 0x00,
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LBR_FORMAT_LIP = 0x01,
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LBR_FORMAT_EIP = 0x02,
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LBR_FORMAT_EIP_FLAGS = 0x03,
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};
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/*
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* Intel LBR_SELECT bits
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* Intel Vol3a, April 2011, Section 16.7 Table 16-10
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*
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* Hardware branch filter (not available on all CPUs)
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*/
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#define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
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#define LBR_USER_BIT 1 /* do not capture at ring > 0 */
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#define LBR_JCC_BIT 2 /* do not capture conditional branches */
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#define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
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#define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
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#define LBR_RETURN_BIT 5 /* do not capture near returns */
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#define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
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#define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
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#define LBR_FAR_BIT 8 /* do not capture far branches */
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#define LBR_KERNEL (1 << LBR_KERNEL_BIT)
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#define LBR_USER (1 << LBR_USER_BIT)
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#define LBR_JCC (1 << LBR_JCC_BIT)
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#define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
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#define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
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#define LBR_RETURN (1 << LBR_RETURN_BIT)
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#define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
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#define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
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#define LBR_FAR (1 << LBR_FAR_BIT)
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#define LBR_PLM (LBR_KERNEL | LBR_USER)
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#define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
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#define LBR_NOT_SUPP -1 /* LBR filter not supported */
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#define LBR_IGN 0 /* ignored */
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#define LBR_ANY \
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(LBR_JCC |\
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LBR_REL_CALL |\
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LBR_IND_CALL |\
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LBR_RETURN |\
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LBR_REL_JMP |\
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LBR_IND_JMP |\
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LBR_FAR)
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#define LBR_FROM_FLAG_MISPRED (1ULL << 63)
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#define for_each_branch_sample_type(x) \
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for ((x) = PERF_SAMPLE_BRANCH_USER; \
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(x) < PERF_SAMPLE_BRANCH_MAX; (x) <<= 1)
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/*
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* x86control flow change classification
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* x86control flow changes include branches, interrupts, traps, faults
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*/
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enum {
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X86_BR_NONE = 0, /* unknown */
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X86_BR_USER = 1 << 0, /* branch target is user */
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X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
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X86_BR_CALL = 1 << 2, /* call */
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X86_BR_RET = 1 << 3, /* return */
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X86_BR_SYSCALL = 1 << 4, /* syscall */
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X86_BR_SYSRET = 1 << 5, /* syscall return */
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X86_BR_INT = 1 << 6, /* sw interrupt */
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X86_BR_IRET = 1 << 7, /* return from interrupt */
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X86_BR_JCC = 1 << 8, /* conditional */
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X86_BR_JMP = 1 << 9, /* jump */
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X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
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X86_BR_IND_CALL = 1 << 11,/* indirect calls */
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};
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#define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
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#define X86_BR_ANY \
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(X86_BR_CALL |\
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X86_BR_RET |\
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X86_BR_SYSCALL |\
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X86_BR_SYSRET |\
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X86_BR_INT |\
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X86_BR_IRET |\
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X86_BR_JCC |\
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X86_BR_JMP |\
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X86_BR_IRQ |\
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X86_BR_IND_CALL)
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#define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
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#define X86_BR_ANY_CALL \
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(X86_BR_CALL |\
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X86_BR_IND_CALL |\
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X86_BR_SYSCALL |\
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X86_BR_IRQ |\
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X86_BR_INT)
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static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
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/*
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* We only support LBR implementations that have FREEZE_LBRS_ON_PMI
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* otherwise it becomes near impossible to get a reliable stack.
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*/
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static void __intel_pmu_lbr_enable(void)
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{
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u64 debugctl;
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (cpuc->lbr_sel)
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wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config);
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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}
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static void __intel_pmu_lbr_disable(void)
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{
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u64 debugctl;
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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}
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static void intel_pmu_lbr_reset_32(void)
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{
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int i;
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for (i = 0; i < x86_pmu.lbr_nr; i++)
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wrmsrl(x86_pmu.lbr_from + i, 0);
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}
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static void intel_pmu_lbr_reset_64(void)
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{
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int i;
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for (i = 0; i < x86_pmu.lbr_nr; i++) {
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wrmsrl(x86_pmu.lbr_from + i, 0);
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wrmsrl(x86_pmu.lbr_to + i, 0);
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}
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}
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void intel_pmu_lbr_reset(void)
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{
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if (!x86_pmu.lbr_nr)
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return;
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if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
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intel_pmu_lbr_reset_32();
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else
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intel_pmu_lbr_reset_64();
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}
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void intel_pmu_lbr_enable(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (!x86_pmu.lbr_nr)
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return;
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/*
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* Reset the LBR stack if we changed task context to
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* avoid data leaks.
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*/
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if (event->ctx->task && cpuc->lbr_context != event->ctx) {
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intel_pmu_lbr_reset();
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cpuc->lbr_context = event->ctx;
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}
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cpuc->br_sel = event->hw.branch_reg.reg;
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cpuc->lbr_users++;
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}
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void intel_pmu_lbr_disable(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (!x86_pmu.lbr_nr)
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return;
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cpuc->lbr_users--;
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WARN_ON_ONCE(cpuc->lbr_users < 0);
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if (cpuc->enabled && !cpuc->lbr_users) {
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__intel_pmu_lbr_disable();
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/* avoid stale pointer */
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cpuc->lbr_context = NULL;
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}
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}
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void intel_pmu_lbr_enable_all(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (cpuc->lbr_users)
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__intel_pmu_lbr_enable();
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}
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void intel_pmu_lbr_disable_all(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (cpuc->lbr_users)
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__intel_pmu_lbr_disable();
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}
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/*
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* TOS = most recently recorded branch
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*/
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static inline u64 intel_pmu_lbr_tos(void)
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{
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u64 tos;
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rdmsrl(x86_pmu.lbr_tos, tos);
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return tos;
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}
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static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
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{
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unsigned long mask = x86_pmu.lbr_nr - 1;
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u64 tos = intel_pmu_lbr_tos();
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int i;
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for (i = 0; i < x86_pmu.lbr_nr; i++) {
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unsigned long lbr_idx = (tos - i) & mask;
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union {
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struct {
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u32 from;
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u32 to;
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};
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u64 lbr;
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} msr_lastbranch;
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rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
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cpuc->lbr_entries[i].from = msr_lastbranch.from;
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cpuc->lbr_entries[i].to = msr_lastbranch.to;
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cpuc->lbr_entries[i].mispred = 0;
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cpuc->lbr_entries[i].predicted = 0;
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cpuc->lbr_entries[i].reserved = 0;
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}
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cpuc->lbr_stack.nr = i;
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}
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/*
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* Due to lack of segmentation in Linux the effective address (offset)
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* is the same as the linear address, allowing us to merge the LIP and EIP
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* LBR formats.
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*/
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static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
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{
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unsigned long mask = x86_pmu.lbr_nr - 1;
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int lbr_format = x86_pmu.intel_cap.lbr_format;
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u64 tos = intel_pmu_lbr_tos();
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int i;
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for (i = 0; i < x86_pmu.lbr_nr; i++) {
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unsigned long lbr_idx = (tos - i) & mask;
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u64 from, to, mis = 0, pred = 0;
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rdmsrl(x86_pmu.lbr_from + lbr_idx, from);
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rdmsrl(x86_pmu.lbr_to + lbr_idx, to);
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if (lbr_format == LBR_FORMAT_EIP_FLAGS) {
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mis = !!(from & LBR_FROM_FLAG_MISPRED);
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pred = !mis;
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from = (u64)((((s64)from) << 1) >> 1);
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}
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cpuc->lbr_entries[i].from = from;
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cpuc->lbr_entries[i].to = to;
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cpuc->lbr_entries[i].mispred = mis;
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cpuc->lbr_entries[i].predicted = pred;
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cpuc->lbr_entries[i].reserved = 0;
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}
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cpuc->lbr_stack.nr = i;
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}
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void intel_pmu_lbr_read(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (!cpuc->lbr_users)
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return;
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if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
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intel_pmu_lbr_read_32(cpuc);
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else
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intel_pmu_lbr_read_64(cpuc);
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intel_pmu_lbr_filter(cpuc);
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}
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/*
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* SW filter is used:
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* - in case there is no HW filter
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* - in case the HW filter has errata or limitations
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*/
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static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
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{
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u64 br_type = event->attr.branch_sample_type;
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int mask = 0;
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if (br_type & PERF_SAMPLE_BRANCH_USER)
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mask |= X86_BR_USER;
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if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
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mask |= X86_BR_KERNEL;
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/* we ignore BRANCH_HV here */
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if (br_type & PERF_SAMPLE_BRANCH_ANY)
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mask |= X86_BR_ANY;
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if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
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mask |= X86_BR_ANY_CALL;
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if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
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mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
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if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
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mask |= X86_BR_IND_CALL;
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/*
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* stash actual user request into reg, it may
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* be used by fixup code for some CPU
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*/
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event->hw.branch_reg.reg = mask;
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}
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/*
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* setup the HW LBR filter
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* Used only when available, may not be enough to disambiguate
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* all branches, may need the help of the SW filter
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*/
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static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
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{
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struct hw_perf_event_extra *reg;
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u64 br_type = event->attr.branch_sample_type;
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u64 mask = 0, m;
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u64 v;
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for_each_branch_sample_type(m) {
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if (!(br_type & m))
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continue;
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v = x86_pmu.lbr_sel_map[m];
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if (v == LBR_NOT_SUPP)
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return -EOPNOTSUPP;
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if (v != LBR_IGN)
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mask |= v;
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}
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reg = &event->hw.branch_reg;
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reg->idx = EXTRA_REG_LBR;
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/* LBR_SELECT operates in suppress mode so invert mask */
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reg->config = ~mask & x86_pmu.lbr_sel_mask;
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return 0;
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}
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int intel_pmu_setup_lbr_filter(struct perf_event *event)
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{
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int ret = 0;
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/*
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* no LBR on this PMU
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*/
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if (!x86_pmu.lbr_nr)
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return -EOPNOTSUPP;
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/*
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* setup SW LBR filter
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*/
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intel_pmu_setup_sw_lbr_filter(event);
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/*
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* setup HW LBR filter, if any
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*/
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if (x86_pmu.lbr_sel_map)
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ret = intel_pmu_setup_hw_lbr_filter(event);
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return ret;
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}
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/*
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* return the type of control flow change at address "from"
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* intruction is not necessarily a branch (in case of interrupt).
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*
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* The branch type returned also includes the priv level of the
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* target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
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*
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* If a branch type is unknown OR the instruction cannot be
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* decoded (e.g., text page not present), then X86_BR_NONE is
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* returned.
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*/
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static int branch_type(unsigned long from, unsigned long to)
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{
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struct insn insn;
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void *addr;
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int bytes, size = MAX_INSN_SIZE;
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int ret = X86_BR_NONE;
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int ext, to_plm, from_plm;
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u8 buf[MAX_INSN_SIZE];
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int is64 = 0;
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to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
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from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
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/*
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* maybe zero if lbr did not fill up after a reset by the time
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* we get a PMU interrupt
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*/
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if (from == 0 || to == 0)
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return X86_BR_NONE;
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if (from_plm == X86_BR_USER) {
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/*
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* can happen if measuring at the user level only
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* and we interrupt in a kernel thread, e.g., idle.
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*/
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if (!current->mm)
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return X86_BR_NONE;
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/* may fail if text not present */
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bytes = copy_from_user_nmi(buf, (void __user *)from, size);
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if (bytes != size)
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return X86_BR_NONE;
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addr = buf;
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} else
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addr = (void *)from;
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/*
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* decoder needs to know the ABI especially
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* on 64-bit systems running 32-bit apps
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*/
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#ifdef CONFIG_X86_64
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is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
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#endif
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insn_init(&insn, addr, is64);
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insn_get_opcode(&insn);
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switch (insn.opcode.bytes[0]) {
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case 0xf:
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switch (insn.opcode.bytes[1]) {
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case 0x05: /* syscall */
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case 0x34: /* sysenter */
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ret = X86_BR_SYSCALL;
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break;
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case 0x07: /* sysret */
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case 0x35: /* sysexit */
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ret = X86_BR_SYSRET;
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break;
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case 0x80 ... 0x8f: /* conditional */
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ret = X86_BR_JCC;
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break;
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default:
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ret = X86_BR_NONE;
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}
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break;
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case 0x70 ... 0x7f: /* conditional */
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ret = X86_BR_JCC;
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break;
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case 0xc2: /* near ret */
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case 0xc3: /* near ret */
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case 0xca: /* far ret */
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case 0xcb: /* far ret */
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ret = X86_BR_RET;
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break;
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case 0xcf: /* iret */
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ret = X86_BR_IRET;
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break;
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case 0xcc ... 0xce: /* int */
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ret = X86_BR_INT;
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break;
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case 0xe8: /* call near rel */
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case 0x9a: /* call far absolute */
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ret = X86_BR_CALL;
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break;
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case 0xe0 ... 0xe3: /* loop jmp */
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ret = X86_BR_JCC;
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|
break;
|
|
case 0xe9 ... 0xeb: /* jmp */
|
|
ret = X86_BR_JMP;
|
|
break;
|
|
case 0xff: /* call near absolute, call far absolute ind */
|
|
insn_get_modrm(&insn);
|
|
ext = (insn.modrm.bytes[0] >> 3) & 0x7;
|
|
switch (ext) {
|
|
case 2: /* near ind call */
|
|
case 3: /* far ind call */
|
|
ret = X86_BR_IND_CALL;
|
|
break;
|
|
case 4:
|
|
case 5:
|
|
ret = X86_BR_JMP;
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
ret = X86_BR_NONE;
|
|
}
|
|
/*
|
|
* interrupts, traps, faults (and thus ring transition) may
|
|
* occur on any instructions. Thus, to classify them correctly,
|
|
* we need to first look at the from and to priv levels. If they
|
|
* are different and to is in the kernel, then it indicates
|
|
* a ring transition. If the from instruction is not a ring
|
|
* transition instr (syscall, systenter, int), then it means
|
|
* it was a irq, trap or fault.
|
|
*
|
|
* we have no way of detecting kernel to kernel faults.
|
|
*/
|
|
if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
|
|
&& ret != X86_BR_SYSCALL && ret != X86_BR_INT)
|
|
ret = X86_BR_IRQ;
|
|
|
|
/*
|
|
* branch priv level determined by target as
|
|
* is done by HW when LBR_SELECT is implemented
|
|
*/
|
|
if (ret != X86_BR_NONE)
|
|
ret |= to_plm;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* implement actual branch filter based on user demand.
|
|
* Hardware may not exactly satisfy that request, thus
|
|
* we need to inspect opcodes. Mismatched branches are
|
|
* discarded. Therefore, the number of branches returned
|
|
* in PERF_SAMPLE_BRANCH_STACK sample may vary.
|
|
*/
|
|
static void
|
|
intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
|
|
{
|
|
u64 from, to;
|
|
int br_sel = cpuc->br_sel;
|
|
int i, j, type;
|
|
bool compress = false;
|
|
|
|
/* if sampling all branches, then nothing to filter */
|
|
if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
|
|
return;
|
|
|
|
for (i = 0; i < cpuc->lbr_stack.nr; i++) {
|
|
|
|
from = cpuc->lbr_entries[i].from;
|
|
to = cpuc->lbr_entries[i].to;
|
|
|
|
type = branch_type(from, to);
|
|
|
|
/* if type does not correspond, then discard */
|
|
if (type == X86_BR_NONE || (br_sel & type) != type) {
|
|
cpuc->lbr_entries[i].from = 0;
|
|
compress = true;
|
|
}
|
|
}
|
|
|
|
if (!compress)
|
|
return;
|
|
|
|
/* remove all entries with from=0 */
|
|
for (i = 0; i < cpuc->lbr_stack.nr; ) {
|
|
if (!cpuc->lbr_entries[i].from) {
|
|
j = i;
|
|
while (++j < cpuc->lbr_stack.nr)
|
|
cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
|
|
cpuc->lbr_stack.nr--;
|
|
if (!cpuc->lbr_entries[i].from)
|
|
continue;
|
|
}
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Map interface branch filters onto LBR filters
|
|
*/
|
|
static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
|
|
[PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
|
|
[PERF_SAMPLE_BRANCH_USER] = LBR_USER,
|
|
[PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
|
|
[PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
|
|
[PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_REL_JMP
|
|
| LBR_IND_JMP | LBR_FAR,
|
|
/*
|
|
* NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
|
|
*/
|
|
[PERF_SAMPLE_BRANCH_ANY_CALL] =
|
|
LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
|
|
/*
|
|
* NHM/WSM erratum: must include IND_JMP to capture IND_CALL
|
|
*/
|
|
[PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP,
|
|
};
|
|
|
|
static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
|
|
[PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
|
|
[PERF_SAMPLE_BRANCH_USER] = LBR_USER,
|
|
[PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
|
|
[PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
|
|
[PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_FAR,
|
|
[PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL
|
|
| LBR_FAR,
|
|
[PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL,
|
|
};
|
|
|
|
/* core */
|
|
void intel_pmu_lbr_init_core(void)
|
|
{
|
|
x86_pmu.lbr_nr = 4;
|
|
x86_pmu.lbr_tos = MSR_LBR_TOS;
|
|
x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
|
|
x86_pmu.lbr_to = MSR_LBR_CORE_TO;
|
|
|
|
/*
|
|
* SW branch filter usage:
|
|
* - compensate for lack of HW filter
|
|
*/
|
|
pr_cont("4-deep LBR, ");
|
|
}
|
|
|
|
/* nehalem/westmere */
|
|
void intel_pmu_lbr_init_nhm(void)
|
|
{
|
|
x86_pmu.lbr_nr = 16;
|
|
x86_pmu.lbr_tos = MSR_LBR_TOS;
|
|
x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
|
|
x86_pmu.lbr_to = MSR_LBR_NHM_TO;
|
|
|
|
x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
|
|
x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
|
|
|
|
/*
|
|
* SW branch filter usage:
|
|
* - workaround LBR_SEL errata (see above)
|
|
* - support syscall, sysret capture.
|
|
* That requires LBR_FAR but that means far
|
|
* jmp need to be filtered out
|
|
*/
|
|
pr_cont("16-deep LBR, ");
|
|
}
|
|
|
|
/* sandy bridge */
|
|
void intel_pmu_lbr_init_snb(void)
|
|
{
|
|
x86_pmu.lbr_nr = 16;
|
|
x86_pmu.lbr_tos = MSR_LBR_TOS;
|
|
x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
|
|
x86_pmu.lbr_to = MSR_LBR_NHM_TO;
|
|
|
|
x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
|
|
x86_pmu.lbr_sel_map = snb_lbr_sel_map;
|
|
|
|
/*
|
|
* SW branch filter usage:
|
|
* - support syscall, sysret capture.
|
|
* That requires LBR_FAR but that means far
|
|
* jmp need to be filtered out
|
|
*/
|
|
pr_cont("16-deep LBR, ");
|
|
}
|
|
|
|
/* atom */
|
|
void intel_pmu_lbr_init_atom(void)
|
|
{
|
|
/*
|
|
* only models starting at stepping 10 seems
|
|
* to have an operational LBR which can freeze
|
|
* on PMU interrupt
|
|
*/
|
|
if (boot_cpu_data.x86_model == 28
|
|
&& boot_cpu_data.x86_mask < 10) {
|
|
pr_cont("LBR disabled due to erratum");
|
|
return;
|
|
}
|
|
|
|
x86_pmu.lbr_nr = 8;
|
|
x86_pmu.lbr_tos = MSR_LBR_TOS;
|
|
x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
|
|
x86_pmu.lbr_to = MSR_LBR_CORE_TO;
|
|
|
|
/*
|
|
* SW branch filter usage:
|
|
* - compensate for lack of HW filter
|
|
*/
|
|
pr_cont("8-deep LBR, ");
|
|
}
|