a120db06c3
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end
stall events.
As explained in Ingo's original comment(8f62242246
), the exact definitions of the stall events are very much processor specific as
different things mean different in their respective instruction pipeline. These
two Power7 raw events are the closest approximation to the concept detailed in
Ingo's comment.
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
It means cycles when the Global Completion Table has no slots from this thread
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
It means no groups completed and GCT not empty for this thread
Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
379 lines
9.6 KiB
C
379 lines
9.6 KiB
C
/*
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* Performance counter support for POWER7 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <linux/string.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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/*
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* Bits in event code for POWER7
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*/
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#define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0xf
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
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#define PM_UNIT_MSK 0xf
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#define PM_COMBINE_SH 11 /* Combined event bit */
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#define PM_COMBINE_MSK 1
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#define PM_COMBINE_MSKS 0x800
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#define PM_L2SEL_SH 8 /* L2 event select */
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#define PM_L2SEL_MSK 7
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#define PM_PMCSEL_MSK 0xff
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/*
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* Bits in MMCR1 for POWER7
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*/
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#define MMCR1_TTM0SEL_SH 60
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#define MMCR1_TTM1SEL_SH 56
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#define MMCR1_TTM2SEL_SH 52
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#define MMCR1_TTM3SEL_SH 48
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#define MMCR1_TTMSEL_MSK 0xf
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#define MMCR1_L2SEL_SH 45
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#define MMCR1_L2SEL_MSK 7
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#define MMCR1_PMC1_COMBINE_SH 35
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#define MMCR1_PMC2_COMBINE_SH 34
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#define MMCR1_PMC3_COMBINE_SH 33
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#define MMCR1_PMC4_COMBINE_SH 32
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#define MMCR1_PMC1SEL_SH 24
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#define MMCR1_PMC2SEL_SH 16
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#define MMCR1_PMC3SEL_SH 8
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#define MMCR1_PMC4SEL_SH 0
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0xff
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/*
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* Layout of constraint bits:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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* [ ><><><><><><>
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* NC P6P5P4P3P2P1
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*
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* NC - number of counters
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* 15: NC error 0x8000
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* 12-14: number of events needing PMC1-4 0x7000
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*
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* P6
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* 11: P6 error 0x800
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* 10-11: Count of events needing PMC6
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*
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* P1..P5
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* 0-9: Count of events needing PMC1..PMC5
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*/
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static int power7_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp)
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{
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int pmc, sh;
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unsigned long mask = 0, value = 0;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 6)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
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return -1;
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}
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if (pmc < 5) {
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/* need a counter from PMC1-4 set */
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mask |= 0x8000;
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value |= 0x1000;
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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#define MAX_ALT 2 /* at most 2 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x200f2, 0x300f2 }, /* PM_INST_DISP */
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{ 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
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{ 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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static int find_alternative(u64 event)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static s64 find_alternative_decode(u64 event)
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{
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int pmc, psel;
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/* this only handles the 4x decode events */
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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psel = event & PM_PMCSEL_MSK;
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if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
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return event - (1 << PM_PMC_SH) + 8;
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if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
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return event + (1 << PM_PMC_SH) - 8;
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return -1;
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}
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static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int i, j, nalt = 1;
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s64 ae;
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alt[0] = event;
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nalt = 1;
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i = find_alternative(event);
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if (i >= 0) {
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for (j = 0; j < MAX_ALT; ++j) {
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ae = event_alternatives[i][j];
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if (ae && ae != event)
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alt[nalt++] = ae;
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}
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} else {
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ae = find_alternative_decode(event);
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if (ae > 0)
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alt[nalt++] = ae;
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}
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if (flags & PPMU_ONLY_COUNT_RUN) {
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/*
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* We're only counting in RUN state,
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* so PM_CYC is equivalent to PM_RUN_CYC
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* and PM_INST_CMPL === PM_RUN_INST_CMPL.
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* This doesn't include alternatives that don't provide
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* any extra flexibility in assigning PMCs.
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*/
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j = nalt;
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for (i = 0; i < nalt; ++i) {
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switch (alt[i]) {
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case 0x1e: /* PM_CYC */
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alt[j++] = 0x600f4; /* PM_RUN_CYC */
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break;
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case 0x600f4: /* PM_RUN_CYC */
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alt[j++] = 0x1e;
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break;
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case 0x2: /* PM_PPC_CMPL */
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alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
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break;
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case 0x500fa: /* PM_RUN_INST_CMPL */
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alt[j++] = 0x2; /* PM_PPC_CMPL */
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break;
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}
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}
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nalt = j;
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}
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return nalt;
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}
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/*
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* Returns 1 if event counts things relating to marked instructions
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* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
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*/
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static int power7_marked_instr_event(u64 event)
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{
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int pmc, psel;
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int unit;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
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if (pmc >= 5)
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return 0;
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switch (psel >> 4) {
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case 2:
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return pmc == 2 || pmc == 4;
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case 3:
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if (psel == 0x3c)
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return pmc == 1;
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if (psel == 0x3e)
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return pmc != 2;
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return 1;
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case 4:
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case 5:
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return unit == 0xd;
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case 6:
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if (psel == 0x64)
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return pmc >= 3;
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case 8:
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return unit == 0xd;
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}
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return 0;
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}
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static int power7_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[])
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{
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unsigned long mmcr1 = 0;
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unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
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unsigned int pmc, unit, combine, l2sel, psel;
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unsigned int pmc_inuse = 0;
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int i;
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/* First pass to count resource use */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 6)
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return -1;
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1;
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pmc_inuse |= 1 << (pmc - 1);
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}
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}
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/* Second pass: assign PMCs, set all MMCR1 fields */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
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combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
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l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
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psel = event[i] & PM_PMCSEL_MSK;
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if (!pmc) {
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/* Bus event or any-PMC direct event */
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for (pmc = 0; pmc < 4; ++pmc) {
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if (!(pmc_inuse & (1 << pmc)))
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break;
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}
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if (pmc >= 4)
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return -1;
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pmc_inuse |= 1 << pmc;
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} else {
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/* Direct or decoded event */
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--pmc;
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}
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if (pmc <= 3) {
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mmcr1 |= (unsigned long) unit
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<< (MMCR1_TTM0SEL_SH - 4 * pmc);
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mmcr1 |= (unsigned long) combine
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<< (MMCR1_PMC1_COMBINE_SH - pmc);
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mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
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if (unit == 6) /* L2 events */
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mmcr1 |= (unsigned long) l2sel
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<< MMCR1_L2SEL_SH;
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}
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if (power7_marked_instr_event(event[i]))
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mmcra |= MMCRA_SAMPLE_ENABLE;
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hwc[i] = pmc;
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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if (pmc_inuse & 1)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0x3e)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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return 0;
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}
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static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
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}
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static int power7_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
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[PERF_COUNT_HW_INSTRUCTIONS] = 2,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/
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[PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0xc880, 0x400f0 },
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[C(OP_WRITE)] = { 0, 0x300f0 },
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[C(OP_PREFETCH)] = { 0xd8b8, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x200fc },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0x408a, 0 },
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},
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[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x16080, 0x26080 },
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[C(OP_WRITE)] = { 0x16082, 0x26082 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x300fc },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x400fc },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x10068, 0x400f6 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { -1, -1 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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static struct power_pmu power7_pmu = {
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.name = "POWER7",
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.n_counter = 6,
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.max_alternatives = MAX_ALT + 1,
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.add_fields = 0x1555ul,
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.test_adder = 0x3000ul,
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.compute_mmcr = power7_compute_mmcr,
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.get_constraint = power7_get_constraint,
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.get_alternatives = power7_get_alternatives,
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.disable_pmc = power7_disable_pmc,
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.flags = PPMU_ALT_SIPR,
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.n_generic = ARRAY_SIZE(power7_generic_events),
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.generic_events = power7_generic_events,
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.cache_events = &power7_cache_events,
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};
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static int __init init_power7_pmu(void)
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{
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if (!cur_cpu_spec->oprofile_cpu_type ||
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strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
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return -ENODEV;
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return register_power_pmu(&power7_pmu);
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}
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early_initcall(init_power7_pmu);
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