2b222a2971
Fixes a handful of sparse warnings. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/hardware/gic.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/mach-types.h>
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#include <mach/msm_iomap.h>
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#include "scm-boot.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
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#define SCSS_CPU1CORE_RESET 0xD80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
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/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
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#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
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extern void msm_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen".
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*/
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volatile int pen_release = -1;
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static DEFINE_SPINLOCK(boot_lock);
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static inline int get_core_count(void)
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{
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/* 1 + the PART[1:0] field of MIDR */
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return ((read_cpuid_id() >> 4) & 3) + 1;
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}
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/* Configure edge-triggered PPIs */
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writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static __cpuinit void prepare_cold_cpu(unsigned int cpu)
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{
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int ret;
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ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
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SCM_FLAG_COLDBOOT_CPU1);
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if (ret == 0) {
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void __iomem *sc1_base_ptr;
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sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
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if (sc1_base_ptr) {
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writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
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writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
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iounmap(sc1_base_ptr);
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}
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} else
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printk(KERN_DEBUG "Failed to set secondary core boot "
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"address\n");
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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static int cold_boot_done;
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/* Only need to bring cpu out of reset this way once */
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if (cold_boot_done == false) {
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prepare_cold_cpu(cpu);
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cold_boot_done = true;
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}
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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pen_release = cpu_logical_map(cpu);
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system. The msm8x60
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* does not support the ARM SCU, so just set the possible cpu mask to
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* NR_CPUS.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores = get_core_count();
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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}
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