7db35f31cb
Several interfaces were missing and others misnumbered or improperly documented. Also, make sure to check the return value when registering the kernel TSBs with the hypervisor. This helped to find the 4MB kernel TSB alignment bug fixed in a previous changeset. Signed-off-by: David S. Miller <davem@davemloft.net>
1919 lines
50 KiB
C
1919 lines
50 KiB
C
/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
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* arch/sparc64/mm/init.c
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*
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* Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/slab.h>
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#include <linux/initrd.h>
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#include <linux/swap.h>
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#include <linux/pagemap.h>
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#include <linux/poison.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/kprobes.h>
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#include <linux/cache.h>
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#include <linux/sort.h>
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#include <linux/percpu.h>
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#include <asm/head.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/oplib.h>
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#include <asm/iommu.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/dma.h>
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#include <asm/starfire.h>
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#include <asm/tlb.h>
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#include <asm/spitfire.h>
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#include <asm/sections.h>
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include <asm/sstate.h>
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#include <asm/mdesc.h>
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#define MAX_PHYS_ADDRESS (1UL << 42UL)
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#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
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#define KPTE_BITMAP_BYTES \
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((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
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unsigned long kern_linear_pte_xor[2] __read_mostly;
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/* A bitmap, one bit for every 256MB of physical memory. If the bit
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* is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
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* if set we should use a 256MB page (via kern_linear_pte_xor[1]).
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*/
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unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
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#ifndef CONFIG_DEBUG_PAGEALLOC
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/* A special kernel TSB for 4MB and 256MB linear mappings.
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* Space is allocated for this right after the trap table
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* in arch/sparc64/kernel/head.S
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*/
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extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
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#endif
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#define MAX_BANKS 32
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static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
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static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
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static int pavail_ents __initdata;
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static int pavail_rescan_ents __initdata;
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static int cmp_p64(const void *a, const void *b)
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{
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const struct linux_prom64_registers *x = a, *y = b;
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if (x->phys_addr > y->phys_addr)
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return 1;
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if (x->phys_addr < y->phys_addr)
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return -1;
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return 0;
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}
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static void __init read_obp_memory(const char *property,
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struct linux_prom64_registers *regs,
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int *num_ents)
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{
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int node = prom_finddevice("/memory");
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int prop_size = prom_getproplen(node, property);
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int ents, ret, i;
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ents = prop_size / sizeof(struct linux_prom64_registers);
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if (ents > MAX_BANKS) {
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prom_printf("The machine has more %s property entries than "
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"this kernel can support (%d).\n",
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property, MAX_BANKS);
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prom_halt();
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}
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ret = prom_getproperty(node, property, (char *) regs, prop_size);
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if (ret == -1) {
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prom_printf("Couldn't get %s property from /memory.\n");
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prom_halt();
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}
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/* Sanitize what we got from the firmware, by page aligning
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* everything.
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*/
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for (i = 0; i < ents; i++) {
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unsigned long base, size;
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base = regs[i].phys_addr;
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size = regs[i].reg_size;
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size &= PAGE_MASK;
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if (base & ~PAGE_MASK) {
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unsigned long new_base = PAGE_ALIGN(base);
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size -= new_base - base;
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if ((long) size < 0L)
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size = 0UL;
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base = new_base;
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}
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if (size == 0UL) {
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/* If it is empty, simply get rid of it.
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* This simplifies the logic of the other
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* functions that process these arrays.
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*/
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memmove(®s[i], ®s[i + 1],
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(ents - i - 1) * sizeof(regs[0]));
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i--;
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ents--;
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continue;
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}
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regs[i].phys_addr = base;
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regs[i].reg_size = size;
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}
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*num_ents = ents;
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sort(regs, ents, sizeof(struct linux_prom64_registers),
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cmp_p64, NULL);
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}
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unsigned long *sparc64_valid_addr_bitmap __read_mostly;
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/* Kernel physical address base and size in bytes. */
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unsigned long kern_base __read_mostly;
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unsigned long kern_size __read_mostly;
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/* Initial ramdisk setup */
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extern unsigned long sparc_ramdisk_image64;
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extern unsigned int sparc_ramdisk_image;
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extern unsigned int sparc_ramdisk_size;
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struct page *mem_map_zero __read_mostly;
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unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
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unsigned long sparc64_kern_pri_context __read_mostly;
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unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
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unsigned long sparc64_kern_sec_context __read_mostly;
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int bigkernel = 0;
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#ifdef CONFIG_DEBUG_DCFLUSH
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atomic_t dcpage_flushes = ATOMIC_INIT(0);
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#ifdef CONFIG_SMP
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atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
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#endif
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#endif
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inline void flush_dcache_page_impl(struct page *page)
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{
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BUG_ON(tlb_type == hypervisor);
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#ifdef CONFIG_DEBUG_DCFLUSH
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atomic_inc(&dcpage_flushes);
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#endif
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#ifdef DCACHE_ALIASING_POSSIBLE
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__flush_dcache_page(page_address(page),
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((tlb_type == spitfire) &&
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page_mapping(page) != NULL));
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#else
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if (page_mapping(page) != NULL &&
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tlb_type == spitfire)
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__flush_icache_page(__pa(page_address(page)));
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#endif
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}
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#define PG_dcache_dirty PG_arch_1
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#define PG_dcache_cpu_shift 32UL
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#define PG_dcache_cpu_mask \
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((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
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#define dcache_dirty_cpu(page) \
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(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
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static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
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{
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unsigned long mask = this_cpu;
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unsigned long non_cpu_bits;
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non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
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mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
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__asm__ __volatile__("1:\n\t"
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"ldx [%2], %%g7\n\t"
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"and %%g7, %1, %%g1\n\t"
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"or %%g1, %0, %%g1\n\t"
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"casx [%2], %%g7, %%g1\n\t"
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"cmp %%g7, %%g1\n\t"
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"membar #StoreLoad | #StoreStore\n\t"
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"bne,pn %%xcc, 1b\n\t"
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" nop"
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: /* no outputs */
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: "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
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: "g1", "g7");
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}
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static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
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{
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unsigned long mask = (1UL << PG_dcache_dirty);
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__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
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"1:\n\t"
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"ldx [%2], %%g7\n\t"
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"srlx %%g7, %4, %%g1\n\t"
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"and %%g1, %3, %%g1\n\t"
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"cmp %%g1, %0\n\t"
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"bne,pn %%icc, 2f\n\t"
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" andn %%g7, %1, %%g1\n\t"
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"casx [%2], %%g7, %%g1\n\t"
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"cmp %%g7, %%g1\n\t"
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"membar #StoreLoad | #StoreStore\n\t"
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"bne,pn %%xcc, 1b\n\t"
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" nop\n"
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"2:"
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: /* no outputs */
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: "r" (cpu), "r" (mask), "r" (&page->flags),
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"i" (PG_dcache_cpu_mask),
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"i" (PG_dcache_cpu_shift)
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: "g1", "g7");
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}
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static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
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{
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unsigned long tsb_addr = (unsigned long) ent;
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if (tlb_type == cheetah_plus || tlb_type == hypervisor)
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tsb_addr = __pa(tsb_addr);
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__tsb_insert(tsb_addr, tag, pte);
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}
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unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
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unsigned long _PAGE_SZBITS __read_mostly;
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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struct mm_struct *mm;
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struct tsb *tsb;
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unsigned long tag, flags;
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unsigned long tsb_index, tsb_hash_shift;
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if (tlb_type != hypervisor) {
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unsigned long pfn = pte_pfn(pte);
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unsigned long pg_flags;
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struct page *page;
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if (pfn_valid(pfn) &&
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(page = pfn_to_page(pfn), page_mapping(page)) &&
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((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
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int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
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PG_dcache_cpu_mask);
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int this_cpu = get_cpu();
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/* This is just to optimize away some function calls
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* in the SMP case.
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*/
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if (cpu == this_cpu)
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flush_dcache_page_impl(page);
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else
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smp_flush_dcache_page_impl(page, cpu);
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clear_dcache_dirty_cpu(page, cpu);
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put_cpu();
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}
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}
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mm = vma->vm_mm;
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tsb_index = MM_TSB_BASE;
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tsb_hash_shift = PAGE_SHIFT;
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spin_lock_irqsave(&mm->context.lock, flags);
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#ifdef CONFIG_HUGETLB_PAGE
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if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
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if ((tlb_type == hypervisor &&
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(pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
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(tlb_type != hypervisor &&
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(pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
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tsb_index = MM_TSB_HUGE;
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tsb_hash_shift = HPAGE_SHIFT;
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}
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}
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#endif
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tsb = mm->context.tsb_block[tsb_index].tsb;
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tsb += ((address >> tsb_hash_shift) &
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(mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
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tag = (address >> 22UL);
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tsb_insert(tsb, tag, pte_val(pte));
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spin_unlock_irqrestore(&mm->context.lock, flags);
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping;
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int this_cpu;
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if (tlb_type == hypervisor)
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return;
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/* Do not bother with the expensive D-cache flush if it
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* is merely the zero page. The 'bigcore' testcase in GDB
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* causes this case to run millions of times.
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*/
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if (page == ZERO_PAGE(0))
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return;
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this_cpu = get_cpu();
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mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping)) {
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int dirty = test_bit(PG_dcache_dirty, &page->flags);
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if (dirty) {
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int dirty_cpu = dcache_dirty_cpu(page);
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if (dirty_cpu == this_cpu)
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goto out;
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smp_flush_dcache_page_impl(page, dirty_cpu);
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}
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set_dcache_dirty(page, this_cpu);
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} else {
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/* We could delay the flush for the !page_mapping
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* case too. But that case is for exec env/arg
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* pages and those are %99 certainly going to get
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* faulted into the tlb (and thus flushed) anyways.
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*/
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flush_dcache_page_impl(page);
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}
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out:
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put_cpu();
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}
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void __kprobes flush_icache_range(unsigned long start, unsigned long end)
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{
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/* Cheetah and Hypervisor platform cpus have coherent I-cache. */
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if (tlb_type == spitfire) {
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unsigned long kaddr;
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/* This code only runs on Spitfire cpus so this is
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* why we can assume _PAGE_PADDR_4U.
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*/
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for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
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unsigned long paddr, mask = _PAGE_PADDR_4U;
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if (kaddr >= PAGE_OFFSET)
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paddr = kaddr & mask;
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else {
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pgd_t *pgdp = pgd_offset_k(kaddr);
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pud_t *pudp = pud_offset(pgdp, kaddr);
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pmd_t *pmdp = pmd_offset(pudp, kaddr);
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pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
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paddr = pte_val(*ptep) & mask;
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}
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__flush_icache_page(paddr);
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}
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}
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}
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void show_mem(void)
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{
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unsigned long total = 0, reserved = 0;
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unsigned long shared = 0, cached = 0;
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pg_data_t *pgdat;
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printk(KERN_INFO "Mem-info:\n");
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show_free_areas();
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printk(KERN_INFO "Free swap: %6ldkB\n",
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nr_swap_pages << (PAGE_SHIFT-10));
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for_each_online_pgdat(pgdat) {
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unsigned long i, flags;
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pgdat_resize_lock(pgdat, &flags);
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for (i = 0; i < pgdat->node_spanned_pages; i++) {
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struct page *page = pgdat_page_nr(pgdat, i);
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total++;
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if (PageReserved(page))
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reserved++;
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else if (PageSwapCache(page))
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cached++;
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else if (page_count(page))
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shared += page_count(page) - 1;
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}
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pgdat_resize_unlock(pgdat, &flags);
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}
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printk(KERN_INFO "%lu pages of RAM\n", total);
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printk(KERN_INFO "%lu reserved pages\n", reserved);
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printk(KERN_INFO "%lu pages shared\n", shared);
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printk(KERN_INFO "%lu pages swap cached\n", cached);
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printk(KERN_INFO "%lu pages dirty\n",
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global_page_state(NR_FILE_DIRTY));
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printk(KERN_INFO "%lu pages writeback\n",
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global_page_state(NR_WRITEBACK));
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printk(KERN_INFO "%lu pages mapped\n",
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global_page_state(NR_FILE_MAPPED));
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printk(KERN_INFO "%lu pages slab\n",
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global_page_state(NR_SLAB_RECLAIMABLE) +
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global_page_state(NR_SLAB_UNRECLAIMABLE));
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printk(KERN_INFO "%lu pages pagetables\n",
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global_page_state(NR_PAGETABLE));
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}
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void mmu_info(struct seq_file *m)
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{
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if (tlb_type == cheetah)
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seq_printf(m, "MMU Type\t: Cheetah\n");
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else if (tlb_type == cheetah_plus)
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seq_printf(m, "MMU Type\t: Cheetah+\n");
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else if (tlb_type == spitfire)
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seq_printf(m, "MMU Type\t: Spitfire\n");
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else if (tlb_type == hypervisor)
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seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
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else
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seq_printf(m, "MMU Type\t: ???\n");
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#ifdef CONFIG_DEBUG_DCFLUSH
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seq_printf(m, "DCPageFlushes\t: %d\n",
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atomic_read(&dcpage_flushes));
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#ifdef CONFIG_SMP
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seq_printf(m, "DCPageFlushesXC\t: %d\n",
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atomic_read(&dcpage_flushes_xcall));
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_DEBUG_DCFLUSH */
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}
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|
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struct linux_prom_translation {
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unsigned long virt;
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unsigned long size;
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unsigned long data;
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};
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|
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/* Exported for kernel TLB miss handling in ktlb.S */
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struct linux_prom_translation prom_trans[512] __read_mostly;
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unsigned int prom_trans_ents __read_mostly;
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|
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/* Exported for SMP bootup purposes. */
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unsigned long kern_locked_tte_data;
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|
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/* The obp translations are saved based on 8k pagesize, since obp can
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* use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
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* HI_OBP_ADDRESS range are handled in ktlb.S.
|
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*/
|
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static inline int in_obp_range(unsigned long vaddr)
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{
|
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return (vaddr >= LOW_OBP_ADDRESS &&
|
|
vaddr < HI_OBP_ADDRESS);
|
|
}
|
|
|
|
static int cmp_ptrans(const void *a, const void *b)
|
|
{
|
|
const struct linux_prom_translation *x = a, *y = b;
|
|
|
|
if (x->virt > y->virt)
|
|
return 1;
|
|
if (x->virt < y->virt)
|
|
return -1;
|
|
return 0;
|
|
}
|
|
|
|
/* Read OBP translations property into 'prom_trans[]'. */
|
|
static void __init read_obp_translations(void)
|
|
{
|
|
int n, node, ents, first, last, i;
|
|
|
|
node = prom_finddevice("/virtual-memory");
|
|
n = prom_getproplen(node, "translations");
|
|
if (unlikely(n == 0 || n == -1)) {
|
|
prom_printf("prom_mappings: Couldn't get size.\n");
|
|
prom_halt();
|
|
}
|
|
if (unlikely(n > sizeof(prom_trans))) {
|
|
prom_printf("prom_mappings: Size %Zd is too big.\n", n);
|
|
prom_halt();
|
|
}
|
|
|
|
if ((n = prom_getproperty(node, "translations",
|
|
(char *)&prom_trans[0],
|
|
sizeof(prom_trans))) == -1) {
|
|
prom_printf("prom_mappings: Couldn't get property.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
n = n / sizeof(struct linux_prom_translation);
|
|
|
|
ents = n;
|
|
|
|
sort(prom_trans, ents, sizeof(struct linux_prom_translation),
|
|
cmp_ptrans, NULL);
|
|
|
|
/* Now kick out all the non-OBP entries. */
|
|
for (i = 0; i < ents; i++) {
|
|
if (in_obp_range(prom_trans[i].virt))
|
|
break;
|
|
}
|
|
first = i;
|
|
for (; i < ents; i++) {
|
|
if (!in_obp_range(prom_trans[i].virt))
|
|
break;
|
|
}
|
|
last = i;
|
|
|
|
for (i = 0; i < (last - first); i++) {
|
|
struct linux_prom_translation *src = &prom_trans[i + first];
|
|
struct linux_prom_translation *dest = &prom_trans[i];
|
|
|
|
*dest = *src;
|
|
}
|
|
for (; i < ents; i++) {
|
|
struct linux_prom_translation *dest = &prom_trans[i];
|
|
dest->virt = dest->size = dest->data = 0x0UL;
|
|
}
|
|
|
|
prom_trans_ents = last - first;
|
|
|
|
if (tlb_type == spitfire) {
|
|
/* Clear diag TTE bits. */
|
|
for (i = 0; i < prom_trans_ents; i++)
|
|
prom_trans[i].data &= ~0x0003fe0000000000UL;
|
|
}
|
|
}
|
|
|
|
static void __init hypervisor_tlb_lock(unsigned long vaddr,
|
|
unsigned long pte,
|
|
unsigned long mmu)
|
|
{
|
|
unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
|
|
|
|
if (ret != 0) {
|
|
prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
|
|
"errors with %lx\n", vaddr, 0, pte, mmu, ret);
|
|
prom_halt();
|
|
}
|
|
}
|
|
|
|
static unsigned long kern_large_tte(unsigned long paddr);
|
|
|
|
static void __init remap_kernel(void)
|
|
{
|
|
unsigned long phys_page, tte_vaddr, tte_data;
|
|
int tlb_ent = sparc64_highest_locked_tlbent();
|
|
|
|
tte_vaddr = (unsigned long) KERNBASE;
|
|
phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
|
|
tte_data = kern_large_tte(phys_page);
|
|
|
|
kern_locked_tte_data = tte_data;
|
|
|
|
/* Now lock us into the TLBs via Hypervisor or OBP. */
|
|
if (tlb_type == hypervisor) {
|
|
hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
|
|
hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
|
|
if (bigkernel) {
|
|
tte_vaddr += 0x400000;
|
|
tte_data += 0x400000;
|
|
hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
|
|
hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
|
|
}
|
|
} else {
|
|
prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
|
|
prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
|
|
if (bigkernel) {
|
|
tlb_ent -= 1;
|
|
prom_dtlb_load(tlb_ent,
|
|
tte_data + 0x400000,
|
|
tte_vaddr + 0x400000);
|
|
prom_itlb_load(tlb_ent,
|
|
tte_data + 0x400000,
|
|
tte_vaddr + 0x400000);
|
|
}
|
|
sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
|
|
}
|
|
if (tlb_type == cheetah_plus) {
|
|
sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
|
|
CTX_CHEETAH_PLUS_NUC);
|
|
sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
|
|
sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
|
|
}
|
|
}
|
|
|
|
|
|
static void __init inherit_prom_mappings(void)
|
|
{
|
|
read_obp_translations();
|
|
|
|
/* Now fixup OBP's idea about where we really are mapped. */
|
|
prom_printf("Remapping the kernel... ");
|
|
remap_kernel();
|
|
prom_printf("done.\n");
|
|
}
|
|
|
|
void prom_world(int enter)
|
|
{
|
|
if (!enter)
|
|
set_fs((mm_segment_t) { get_thread_current_ds() });
|
|
|
|
__asm__ __volatile__("flushw");
|
|
}
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
void __flush_dcache_range(unsigned long start, unsigned long end)
|
|
{
|
|
unsigned long va;
|
|
|
|
if (tlb_type == spitfire) {
|
|
int n = 0;
|
|
|
|
for (va = start; va < end; va += 32) {
|
|
spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
|
|
if (++n >= 512)
|
|
break;
|
|
}
|
|
} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
|
|
start = __pa(start);
|
|
end = __pa(end);
|
|
for (va = start; va < end; va += 32)
|
|
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
|
"membar #Sync"
|
|
: /* no outputs */
|
|
: "r" (va),
|
|
"i" (ASI_DCACHE_INVALIDATE));
|
|
}
|
|
}
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
/* get_new_mmu_context() uses "cache + 1". */
|
|
DEFINE_SPINLOCK(ctx_alloc_lock);
|
|
unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
|
|
#define MAX_CTX_NR (1UL << CTX_NR_BITS)
|
|
#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
|
|
DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
|
|
|
|
/* Caller does TLB context flushing on local CPU if necessary.
|
|
* The caller also ensures that CTX_VALID(mm->context) is false.
|
|
*
|
|
* We must be careful about boundary cases so that we never
|
|
* let the user have CTX 0 (nucleus) or we ever use a CTX
|
|
* version of zero (and thus NO_CONTEXT would not be caught
|
|
* by version mis-match tests in mmu_context.h).
|
|
*
|
|
* Always invoked with interrupts disabled.
|
|
*/
|
|
void get_new_mmu_context(struct mm_struct *mm)
|
|
{
|
|
unsigned long ctx, new_ctx;
|
|
unsigned long orig_pgsz_bits;
|
|
unsigned long flags;
|
|
int new_version;
|
|
|
|
spin_lock_irqsave(&ctx_alloc_lock, flags);
|
|
orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
|
|
ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
|
|
new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
|
|
new_version = 0;
|
|
if (new_ctx >= (1 << CTX_NR_BITS)) {
|
|
new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
|
|
if (new_ctx >= ctx) {
|
|
int i;
|
|
new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
|
|
CTX_FIRST_VERSION;
|
|
if (new_ctx == 1)
|
|
new_ctx = CTX_FIRST_VERSION;
|
|
|
|
/* Don't call memset, for 16 entries that's just
|
|
* plain silly...
|
|
*/
|
|
mmu_context_bmap[0] = 3;
|
|
mmu_context_bmap[1] = 0;
|
|
mmu_context_bmap[2] = 0;
|
|
mmu_context_bmap[3] = 0;
|
|
for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
|
|
mmu_context_bmap[i + 0] = 0;
|
|
mmu_context_bmap[i + 1] = 0;
|
|
mmu_context_bmap[i + 2] = 0;
|
|
mmu_context_bmap[i + 3] = 0;
|
|
}
|
|
new_version = 1;
|
|
goto out;
|
|
}
|
|
}
|
|
mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
|
|
new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
|
|
out:
|
|
tlb_context_cache = new_ctx;
|
|
mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
|
|
spin_unlock_irqrestore(&ctx_alloc_lock, flags);
|
|
|
|
if (unlikely(new_version))
|
|
smp_new_mmu_context_version();
|
|
}
|
|
|
|
/* Find a free area for the bootmem map, avoiding the kernel image
|
|
* and the initial ramdisk.
|
|
*/
|
|
static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
|
|
unsigned long end_pfn)
|
|
{
|
|
unsigned long avoid_start, avoid_end, bootmap_size;
|
|
int i;
|
|
|
|
bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
|
|
bootmap_size <<= PAGE_SHIFT;
|
|
|
|
avoid_start = avoid_end = 0;
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
avoid_start = initrd_start;
|
|
avoid_end = PAGE_ALIGN(initrd_end);
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
|
|
kern_base, PAGE_ALIGN(kern_base + kern_size),
|
|
avoid_start, avoid_end);
|
|
#endif
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
unsigned long start, end;
|
|
|
|
start = pavail[i].phys_addr;
|
|
end = start + pavail[i].reg_size;
|
|
|
|
while (start < end) {
|
|
if (start >= kern_base &&
|
|
start < PAGE_ALIGN(kern_base + kern_size)) {
|
|
start = PAGE_ALIGN(kern_base + kern_size);
|
|
continue;
|
|
}
|
|
if (start >= avoid_start && start < avoid_end) {
|
|
start = avoid_end;
|
|
continue;
|
|
}
|
|
|
|
if ((end - start) < bootmap_size)
|
|
break;
|
|
|
|
if (start < kern_base &&
|
|
(start + bootmap_size) > kern_base) {
|
|
start = PAGE_ALIGN(kern_base + kern_size);
|
|
continue;
|
|
}
|
|
|
|
if (start < avoid_start &&
|
|
(start + bootmap_size) > avoid_start) {
|
|
start = avoid_end;
|
|
continue;
|
|
}
|
|
|
|
/* OK, it doesn't overlap anything, use it. */
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
|
|
start >> PAGE_SHIFT, start);
|
|
#endif
|
|
return start >> PAGE_SHIFT;
|
|
}
|
|
}
|
|
|
|
prom_printf("Cannot find free area for bootmap, aborting.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
static void __init trim_pavail(unsigned long *cur_size_p,
|
|
unsigned long *end_of_phys_p)
|
|
{
|
|
unsigned long to_trim = *cur_size_p - cmdline_memory_size;
|
|
unsigned long avoid_start, avoid_end;
|
|
int i;
|
|
|
|
to_trim = PAGE_ALIGN(to_trim);
|
|
|
|
avoid_start = avoid_end = 0;
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
avoid_start = initrd_start;
|
|
avoid_end = PAGE_ALIGN(initrd_end);
|
|
#endif
|
|
|
|
/* Trim some pavail[] entries in order to satisfy the
|
|
* requested "mem=xxx" kernel command line specification.
|
|
*
|
|
* We must not trim off the kernel image area nor the
|
|
* initial ramdisk range (if any). Also, we must not trim
|
|
* any pavail[] entry down to zero in order to preserve
|
|
* the invariant that all pavail[] entries have a non-zero
|
|
* size which is assumed by all of the code in here.
|
|
*/
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
unsigned long start, end, kern_end;
|
|
unsigned long trim_low, trim_high, n;
|
|
|
|
kern_end = PAGE_ALIGN(kern_base + kern_size);
|
|
|
|
trim_low = start = pavail[i].phys_addr;
|
|
trim_high = end = start + pavail[i].reg_size;
|
|
|
|
if (kern_base >= start &&
|
|
kern_base < end) {
|
|
trim_low = kern_base;
|
|
if (kern_end >= end)
|
|
continue;
|
|
}
|
|
if (kern_end >= start &&
|
|
kern_end < end) {
|
|
trim_high = kern_end;
|
|
}
|
|
if (avoid_start &&
|
|
avoid_start >= start &&
|
|
avoid_start < end) {
|
|
if (trim_low > avoid_start)
|
|
trim_low = avoid_start;
|
|
if (avoid_end >= end)
|
|
continue;
|
|
}
|
|
if (avoid_end &&
|
|
avoid_end >= start &&
|
|
avoid_end < end) {
|
|
if (trim_high < avoid_end)
|
|
trim_high = avoid_end;
|
|
}
|
|
|
|
if (trim_high <= trim_low)
|
|
continue;
|
|
|
|
if (trim_low == start && trim_high == end) {
|
|
/* Whole chunk is available for trimming.
|
|
* Trim all except one page, in order to keep
|
|
* entry non-empty.
|
|
*/
|
|
n = (end - start) - PAGE_SIZE;
|
|
if (n > to_trim)
|
|
n = to_trim;
|
|
|
|
if (n) {
|
|
pavail[i].phys_addr += n;
|
|
pavail[i].reg_size -= n;
|
|
to_trim -= n;
|
|
}
|
|
} else {
|
|
n = (trim_low - start);
|
|
if (n > to_trim)
|
|
n = to_trim;
|
|
|
|
if (n) {
|
|
pavail[i].phys_addr += n;
|
|
pavail[i].reg_size -= n;
|
|
to_trim -= n;
|
|
}
|
|
if (to_trim) {
|
|
n = end - trim_high;
|
|
if (n > to_trim)
|
|
n = to_trim;
|
|
if (n) {
|
|
pavail[i].reg_size -= n;
|
|
to_trim -= n;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!to_trim)
|
|
break;
|
|
}
|
|
|
|
/* Recalculate. */
|
|
*cur_size_p = 0UL;
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
*end_of_phys_p = pavail[i].phys_addr +
|
|
pavail[i].reg_size;
|
|
*cur_size_p += pavail[i].reg_size;
|
|
}
|
|
}
|
|
|
|
/* About pages_avail, this is the value we will use to calculate
|
|
* the zholes_size[] argument given to free_area_init_node(). The
|
|
* page allocator uses this to calculate nr_kernel_pages,
|
|
* nr_all_pages and zone->present_pages. On NUMA it is used
|
|
* to calculate zone->min_unmapped_pages and zone->min_slab_pages.
|
|
*
|
|
* So this number should really be set to what the page allocator
|
|
* actually ends up with. This means:
|
|
* 1) It should include bootmem map pages, we'll release those.
|
|
* 2) It should not include the kernel image, except for the
|
|
* __init sections which we will also release.
|
|
* 3) It should include the initrd image, since we'll release
|
|
* that too.
|
|
*/
|
|
static unsigned long __init bootmem_init(unsigned long *pages_avail,
|
|
unsigned long phys_base)
|
|
{
|
|
unsigned long bootmap_size, end_pfn;
|
|
unsigned long end_of_phys_memory = 0UL;
|
|
unsigned long bootmap_pfn, bytes_avail, size;
|
|
int i;
|
|
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("bootmem_init: Scan pavail, ");
|
|
#endif
|
|
|
|
bytes_avail = 0UL;
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
end_of_phys_memory = pavail[i].phys_addr +
|
|
pavail[i].reg_size;
|
|
bytes_avail += pavail[i].reg_size;
|
|
}
|
|
|
|
/* Determine the location of the initial ramdisk before trying
|
|
* to honor the "mem=xxx" command line argument. We must know
|
|
* where the kernel image and the ramdisk image are so that we
|
|
* do not trim those two areas from the physical memory map.
|
|
*/
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
/* Now have to check initial ramdisk, so that bootmap does not overwrite it */
|
|
if (sparc_ramdisk_image || sparc_ramdisk_image64) {
|
|
unsigned long ramdisk_image = sparc_ramdisk_image ?
|
|
sparc_ramdisk_image : sparc_ramdisk_image64;
|
|
ramdisk_image -= KERNBASE;
|
|
initrd_start = ramdisk_image + phys_base;
|
|
initrd_end = initrd_start + sparc_ramdisk_size;
|
|
if (initrd_end > end_of_phys_memory) {
|
|
printk(KERN_CRIT "initrd extends beyond end of memory "
|
|
"(0x%016lx > 0x%016lx)\ndisabling initrd\n",
|
|
initrd_end, end_of_phys_memory);
|
|
initrd_start = 0;
|
|
initrd_end = 0;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (cmdline_memory_size &&
|
|
bytes_avail > cmdline_memory_size)
|
|
trim_pavail(&bytes_avail,
|
|
&end_of_phys_memory);
|
|
|
|
*pages_avail = bytes_avail >> PAGE_SHIFT;
|
|
|
|
end_pfn = end_of_phys_memory >> PAGE_SHIFT;
|
|
|
|
/* Initialize the boot-time allocator. */
|
|
max_pfn = max_low_pfn = end_pfn;
|
|
min_low_pfn = (phys_base >> PAGE_SHIFT);
|
|
|
|
bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
|
|
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
|
|
min_low_pfn, bootmap_pfn, max_low_pfn);
|
|
#endif
|
|
bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
|
|
min_low_pfn, end_pfn);
|
|
|
|
/* Now register the available physical memory with the
|
|
* allocator.
|
|
*/
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
|
|
i, pavail[i].phys_addr, pavail[i].reg_size);
|
|
#endif
|
|
free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
if (initrd_start) {
|
|
size = initrd_end - initrd_start;
|
|
|
|
/* Reserve the initrd image area. */
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
|
|
initrd_start, initrd_end);
|
|
#endif
|
|
reserve_bootmem(initrd_start, size);
|
|
|
|
initrd_start += PAGE_OFFSET;
|
|
initrd_end += PAGE_OFFSET;
|
|
}
|
|
#endif
|
|
/* Reserve the kernel text/data/bss. */
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
|
|
#endif
|
|
reserve_bootmem(kern_base, kern_size);
|
|
*pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
|
|
|
|
/* Add back in the initmem pages. */
|
|
size = ((unsigned long)(__init_end) & PAGE_MASK) -
|
|
PAGE_ALIGN((unsigned long)__init_begin);
|
|
*pages_avail += size >> PAGE_SHIFT;
|
|
|
|
/* Reserve the bootmem map. We do not account for it
|
|
* in pages_avail because we will release that memory
|
|
* in free_all_bootmem.
|
|
*/
|
|
size = bootmap_size;
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
|
|
(bootmap_pfn << PAGE_SHIFT), size);
|
|
#endif
|
|
reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
|
|
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
unsigned long start_pfn, end_pfn;
|
|
|
|
start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
|
|
end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("memory_present(0, %lx, %lx)\n",
|
|
start_pfn, end_pfn);
|
|
#endif
|
|
memory_present(0, start_pfn, end_pfn);
|
|
}
|
|
|
|
sparse_init();
|
|
|
|
return end_pfn;
|
|
}
|
|
|
|
static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
|
|
static int pall_ents __initdata;
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
|
|
{
|
|
unsigned long vstart = PAGE_OFFSET + pstart;
|
|
unsigned long vend = PAGE_OFFSET + pend;
|
|
unsigned long alloc_bytes = 0UL;
|
|
|
|
if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
|
|
prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
|
|
vstart, vend);
|
|
prom_halt();
|
|
}
|
|
|
|
while (vstart < vend) {
|
|
unsigned long this_end, paddr = __pa(vstart);
|
|
pgd_t *pgd = pgd_offset_k(vstart);
|
|
pud_t *pud;
|
|
pmd_t *pmd;
|
|
pte_t *pte;
|
|
|
|
pud = pud_offset(pgd, vstart);
|
|
if (pud_none(*pud)) {
|
|
pmd_t *new;
|
|
|
|
new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
|
|
alloc_bytes += PAGE_SIZE;
|
|
pud_populate(&init_mm, pud, new);
|
|
}
|
|
|
|
pmd = pmd_offset(pud, vstart);
|
|
if (!pmd_present(*pmd)) {
|
|
pte_t *new;
|
|
|
|
new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
|
|
alloc_bytes += PAGE_SIZE;
|
|
pmd_populate_kernel(&init_mm, pmd, new);
|
|
}
|
|
|
|
pte = pte_offset_kernel(pmd, vstart);
|
|
this_end = (vstart + PMD_SIZE) & PMD_MASK;
|
|
if (this_end > vend)
|
|
this_end = vend;
|
|
|
|
while (vstart < this_end) {
|
|
pte_val(*pte) = (paddr | pgprot_val(prot));
|
|
|
|
vstart += PAGE_SIZE;
|
|
paddr += PAGE_SIZE;
|
|
pte++;
|
|
}
|
|
}
|
|
|
|
return alloc_bytes;
|
|
}
|
|
|
|
extern unsigned int kvmap_linear_patch[1];
|
|
#endif /* CONFIG_DEBUG_PAGEALLOC */
|
|
|
|
static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
|
|
{
|
|
const unsigned long shift_256MB = 28;
|
|
const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
|
|
const unsigned long size_256MB = (1UL << shift_256MB);
|
|
|
|
while (start < end) {
|
|
long remains;
|
|
|
|
remains = end - start;
|
|
if (remains < size_256MB)
|
|
break;
|
|
|
|
if (start & mask_256MB) {
|
|
start = (start + size_256MB) & ~mask_256MB;
|
|
continue;
|
|
}
|
|
|
|
while (remains >= size_256MB) {
|
|
unsigned long index = start >> shift_256MB;
|
|
|
|
__set_bit(index, kpte_linear_bitmap);
|
|
|
|
start += size_256MB;
|
|
remains -= size_256MB;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void __init kernel_physical_mapping_init(void)
|
|
{
|
|
unsigned long i;
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
unsigned long mem_alloced = 0UL;
|
|
#endif
|
|
|
|
read_obp_memory("reg", &pall[0], &pall_ents);
|
|
|
|
for (i = 0; i < pall_ents; i++) {
|
|
unsigned long phys_start, phys_end;
|
|
|
|
phys_start = pall[i].phys_addr;
|
|
phys_end = phys_start + pall[i].reg_size;
|
|
|
|
mark_kpte_bitmap(phys_start, phys_end);
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
mem_alloced += kernel_map_range(phys_start, phys_end,
|
|
PAGE_KERNEL);
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
printk("Allocated %ld bytes for kernel page tables.\n",
|
|
mem_alloced);
|
|
|
|
kvmap_linear_patch[0] = 0x01000000; /* nop */
|
|
flushi(&kvmap_linear_patch[0]);
|
|
|
|
__flush_tlb_all();
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
void kernel_map_pages(struct page *page, int numpages, int enable)
|
|
{
|
|
unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
|
|
unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
|
|
|
|
kernel_map_range(phys_start, phys_end,
|
|
(enable ? PAGE_KERNEL : __pgprot(0)));
|
|
|
|
flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
|
|
PAGE_OFFSET + phys_end);
|
|
|
|
/* we should perform an IPI and flush all tlbs,
|
|
* but that can deadlock->flush only current cpu.
|
|
*/
|
|
__flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
|
|
PAGE_OFFSET + phys_end);
|
|
}
|
|
#endif
|
|
|
|
unsigned long __init find_ecache_flush_span(unsigned long size)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
if (pavail[i].reg_size >= size)
|
|
return pavail[i].phys_addr;
|
|
}
|
|
|
|
return ~0UL;
|
|
}
|
|
|
|
static void __init tsb_phys_patch(void)
|
|
{
|
|
struct tsb_ldquad_phys_patch_entry *pquad;
|
|
struct tsb_phys_patch_entry *p;
|
|
|
|
pquad = &__tsb_ldquad_phys_patch;
|
|
while (pquad < &__tsb_ldquad_phys_patch_end) {
|
|
unsigned long addr = pquad->addr;
|
|
|
|
if (tlb_type == hypervisor)
|
|
*(unsigned int *) addr = pquad->sun4v_insn;
|
|
else
|
|
*(unsigned int *) addr = pquad->sun4u_insn;
|
|
wmb();
|
|
__asm__ __volatile__("flush %0"
|
|
: /* no outputs */
|
|
: "r" (addr));
|
|
|
|
pquad++;
|
|
}
|
|
|
|
p = &__tsb_phys_patch;
|
|
while (p < &__tsb_phys_patch_end) {
|
|
unsigned long addr = p->addr;
|
|
|
|
*(unsigned int *) addr = p->insn;
|
|
wmb();
|
|
__asm__ __volatile__("flush %0"
|
|
: /* no outputs */
|
|
: "r" (addr));
|
|
|
|
p++;
|
|
}
|
|
}
|
|
|
|
/* Don't mark as init, we give this to the Hypervisor. */
|
|
#ifndef CONFIG_DEBUG_PAGEALLOC
|
|
#define NUM_KTSB_DESCR 2
|
|
#else
|
|
#define NUM_KTSB_DESCR 1
|
|
#endif
|
|
static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
|
|
extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
|
|
|
|
static void __init sun4v_ktsb_init(void)
|
|
{
|
|
unsigned long ktsb_pa;
|
|
|
|
/* First KTSB for PAGE_SIZE mappings. */
|
|
ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
|
|
|
|
switch (PAGE_SIZE) {
|
|
case 8 * 1024:
|
|
default:
|
|
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
|
|
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
|
|
break;
|
|
|
|
case 64 * 1024:
|
|
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
|
|
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
|
|
break;
|
|
|
|
case 512 * 1024:
|
|
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
|
|
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
|
|
break;
|
|
|
|
case 4 * 1024 * 1024:
|
|
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
|
|
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
|
|
break;
|
|
};
|
|
|
|
ktsb_descr[0].assoc = 1;
|
|
ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
|
|
ktsb_descr[0].ctx_idx = 0;
|
|
ktsb_descr[0].tsb_base = ktsb_pa;
|
|
ktsb_descr[0].resv = 0;
|
|
|
|
#ifndef CONFIG_DEBUG_PAGEALLOC
|
|
/* Second KTSB for 4MB/256MB mappings. */
|
|
ktsb_pa = (kern_base +
|
|
((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
|
|
|
|
ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
|
|
ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
|
|
HV_PGSZ_MASK_256MB);
|
|
ktsb_descr[1].assoc = 1;
|
|
ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
|
|
ktsb_descr[1].ctx_idx = 0;
|
|
ktsb_descr[1].tsb_base = ktsb_pa;
|
|
ktsb_descr[1].resv = 0;
|
|
#endif
|
|
}
|
|
|
|
void __cpuinit sun4v_ktsb_register(void)
|
|
{
|
|
unsigned long pa, ret;
|
|
|
|
pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
|
|
|
|
ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
|
|
if (ret != 0) {
|
|
prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
|
|
"errors with %lx\n", pa, ret);
|
|
prom_halt();
|
|
}
|
|
}
|
|
|
|
/* paging_init() sets up the page tables */
|
|
|
|
extern void cheetah_ecache_flush_init(void);
|
|
extern void sun4v_patch_tlb_handlers(void);
|
|
|
|
extern void cpu_probe(void);
|
|
extern void central_probe(void);
|
|
|
|
static unsigned long last_valid_pfn;
|
|
pgd_t swapper_pg_dir[2048];
|
|
|
|
static void sun4u_pgprot_init(void);
|
|
static void sun4v_pgprot_init(void);
|
|
|
|
void __init paging_init(void)
|
|
{
|
|
unsigned long end_pfn, pages_avail, shift, phys_base;
|
|
unsigned long real_end, i;
|
|
|
|
/* These build time checkes make sure that the dcache_dirty_cpu()
|
|
* page->flags usage will work.
|
|
*
|
|
* When a page gets marked as dcache-dirty, we store the
|
|
* cpu number starting at bit 32 in the page->flags. Also,
|
|
* functions like clear_dcache_dirty_cpu use the cpu mask
|
|
* in 13-bit signed-immediate instruction fields.
|
|
*/
|
|
BUILD_BUG_ON(FLAGS_RESERVED != 32);
|
|
BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
|
|
ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
|
|
BUILD_BUG_ON(NR_CPUS > 4096);
|
|
|
|
kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
|
|
kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
|
|
|
|
sstate_booting();
|
|
|
|
/* Invalidate both kernel TSBs. */
|
|
memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
|
|
#ifndef CONFIG_DEBUG_PAGEALLOC
|
|
memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
|
|
#endif
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_pgprot_init();
|
|
else
|
|
sun4u_pgprot_init();
|
|
|
|
if (tlb_type == cheetah_plus ||
|
|
tlb_type == hypervisor)
|
|
tsb_phys_patch();
|
|
|
|
if (tlb_type == hypervisor) {
|
|
sun4v_patch_tlb_handlers();
|
|
sun4v_ktsb_init();
|
|
}
|
|
|
|
/* Find available physical memory... */
|
|
read_obp_memory("available", &pavail[0], &pavail_ents);
|
|
|
|
phys_base = 0xffffffffffffffffUL;
|
|
for (i = 0; i < pavail_ents; i++)
|
|
phys_base = min(phys_base, pavail[i].phys_addr);
|
|
|
|
set_bit(0, mmu_context_bmap);
|
|
|
|
shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
|
|
|
|
real_end = (unsigned long)_end;
|
|
if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
|
|
bigkernel = 1;
|
|
if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
|
|
prom_printf("paging_init: Kernel > 8MB, too large.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
/* Set kernel pgd to upper alias so physical page computations
|
|
* work.
|
|
*/
|
|
init_mm.pgd += ((shift) / (sizeof(pgd_t)));
|
|
|
|
memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
|
|
|
|
/* Now can init the kernel/bad page tables. */
|
|
pud_set(pud_offset(&swapper_pg_dir[0], 0),
|
|
swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
|
|
|
|
inherit_prom_mappings();
|
|
|
|
/* Ok, we can use our TLB miss and window trap handlers safely. */
|
|
setup_tba();
|
|
|
|
__flush_tlb_all();
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_ktsb_register();
|
|
|
|
/* Setup bootmem... */
|
|
pages_avail = 0;
|
|
last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
|
|
|
|
max_mapnr = last_valid_pfn;
|
|
|
|
kernel_physical_mapping_init();
|
|
|
|
real_setup_per_cpu_areas();
|
|
|
|
prom_build_devicetree();
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_mdesc_init();
|
|
|
|
{
|
|
unsigned long zones_size[MAX_NR_ZONES];
|
|
unsigned long zholes_size[MAX_NR_ZONES];
|
|
int znum;
|
|
|
|
for (znum = 0; znum < MAX_NR_ZONES; znum++)
|
|
zones_size[znum] = zholes_size[znum] = 0;
|
|
|
|
zones_size[ZONE_NORMAL] = end_pfn;
|
|
zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
|
|
|
|
free_area_init_node(0, &contig_page_data, zones_size,
|
|
__pa(PAGE_OFFSET) >> PAGE_SHIFT,
|
|
zholes_size);
|
|
}
|
|
|
|
prom_printf("Booting Linux...\n");
|
|
|
|
central_probe();
|
|
cpu_probe();
|
|
}
|
|
|
|
static void __init taint_real_pages(void)
|
|
{
|
|
int i;
|
|
|
|
read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
|
|
|
|
/* Find changes discovered in the physmem available rescan and
|
|
* reserve the lost portions in the bootmem maps.
|
|
*/
|
|
for (i = 0; i < pavail_ents; i++) {
|
|
unsigned long old_start, old_end;
|
|
|
|
old_start = pavail[i].phys_addr;
|
|
old_end = old_start +
|
|
pavail[i].reg_size;
|
|
while (old_start < old_end) {
|
|
int n;
|
|
|
|
for (n = 0; n < pavail_rescan_ents; n++) {
|
|
unsigned long new_start, new_end;
|
|
|
|
new_start = pavail_rescan[n].phys_addr;
|
|
new_end = new_start +
|
|
pavail_rescan[n].reg_size;
|
|
|
|
if (new_start <= old_start &&
|
|
new_end >= (old_start + PAGE_SIZE)) {
|
|
set_bit(old_start >> 22,
|
|
sparc64_valid_addr_bitmap);
|
|
goto do_next_page;
|
|
}
|
|
}
|
|
reserve_bootmem(old_start, PAGE_SIZE);
|
|
|
|
do_next_page:
|
|
old_start += PAGE_SIZE;
|
|
}
|
|
}
|
|
}
|
|
|
|
int __init page_in_phys_avail(unsigned long paddr)
|
|
{
|
|
int i;
|
|
|
|
paddr &= PAGE_MASK;
|
|
|
|
for (i = 0; i < pavail_rescan_ents; i++) {
|
|
unsigned long start, end;
|
|
|
|
start = pavail_rescan[i].phys_addr;
|
|
end = start + pavail_rescan[i].reg_size;
|
|
|
|
if (paddr >= start && paddr < end)
|
|
return 1;
|
|
}
|
|
if (paddr >= kern_base && paddr < (kern_base + kern_size))
|
|
return 1;
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
if (paddr >= __pa(initrd_start) &&
|
|
paddr < __pa(PAGE_ALIGN(initrd_end)))
|
|
return 1;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init mem_init(void)
|
|
{
|
|
unsigned long codepages, datapages, initpages;
|
|
unsigned long addr, last;
|
|
int i;
|
|
|
|
i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
|
|
i += 1;
|
|
sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
|
|
if (sparc64_valid_addr_bitmap == NULL) {
|
|
prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
|
|
prom_halt();
|
|
}
|
|
memset(sparc64_valid_addr_bitmap, 0, i << 3);
|
|
|
|
addr = PAGE_OFFSET + kern_base;
|
|
last = PAGE_ALIGN(kern_size) + addr;
|
|
while (addr < last) {
|
|
set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
|
|
addr += PAGE_SIZE;
|
|
}
|
|
|
|
taint_real_pages();
|
|
|
|
high_memory = __va(last_valid_pfn << PAGE_SHIFT);
|
|
|
|
#ifdef CONFIG_DEBUG_BOOTMEM
|
|
prom_printf("mem_init: Calling free_all_bootmem().\n");
|
|
#endif
|
|
|
|
/* We subtract one to account for the mem_map_zero page
|
|
* allocated below.
|
|
*/
|
|
totalram_pages = num_physpages = free_all_bootmem() - 1;
|
|
|
|
/*
|
|
* Set up the zero page, mark it reserved, so that page count
|
|
* is not manipulated when freeing the page from user ptes.
|
|
*/
|
|
mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
|
|
if (mem_map_zero == NULL) {
|
|
prom_printf("paging_init: Cannot alloc zero page.\n");
|
|
prom_halt();
|
|
}
|
|
SetPageReserved(mem_map_zero);
|
|
|
|
codepages = (((unsigned long) _etext) - ((unsigned long) _start));
|
|
codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
|
|
datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
|
|
datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
|
|
initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
|
|
initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
|
|
|
|
printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
|
|
nr_free_pages() << (PAGE_SHIFT-10),
|
|
codepages << (PAGE_SHIFT-10),
|
|
datapages << (PAGE_SHIFT-10),
|
|
initpages << (PAGE_SHIFT-10),
|
|
PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
|
|
|
|
if (tlb_type == cheetah || tlb_type == cheetah_plus)
|
|
cheetah_ecache_flush_init();
|
|
}
|
|
|
|
void free_initmem(void)
|
|
{
|
|
unsigned long addr, initend;
|
|
|
|
/*
|
|
* The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
|
|
*/
|
|
addr = PAGE_ALIGN((unsigned long)(__init_begin));
|
|
initend = (unsigned long)(__init_end) & PAGE_MASK;
|
|
for (; addr < initend; addr += PAGE_SIZE) {
|
|
unsigned long page;
|
|
struct page *p;
|
|
|
|
page = (addr +
|
|
((unsigned long) __va(kern_base)) -
|
|
((unsigned long) KERNBASE));
|
|
memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
|
p = virt_to_page(page);
|
|
|
|
ClearPageReserved(p);
|
|
init_page_count(p);
|
|
__free_page(p);
|
|
num_physpages++;
|
|
totalram_pages++;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
void free_initrd_mem(unsigned long start, unsigned long end)
|
|
{
|
|
if (start < end)
|
|
printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
|
|
for (; start < end; start += PAGE_SIZE) {
|
|
struct page *p = virt_to_page(start);
|
|
|
|
ClearPageReserved(p);
|
|
init_page_count(p);
|
|
__free_page(p);
|
|
num_physpages++;
|
|
totalram_pages++;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
|
|
#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
|
|
#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
|
|
#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
|
|
#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
|
|
#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
|
|
|
|
pgprot_t PAGE_KERNEL __read_mostly;
|
|
EXPORT_SYMBOL(PAGE_KERNEL);
|
|
|
|
pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
|
|
pgprot_t PAGE_COPY __read_mostly;
|
|
|
|
pgprot_t PAGE_SHARED __read_mostly;
|
|
EXPORT_SYMBOL(PAGE_SHARED);
|
|
|
|
pgprot_t PAGE_EXEC __read_mostly;
|
|
unsigned long pg_iobits __read_mostly;
|
|
|
|
unsigned long _PAGE_IE __read_mostly;
|
|
EXPORT_SYMBOL(_PAGE_IE);
|
|
|
|
unsigned long _PAGE_E __read_mostly;
|
|
EXPORT_SYMBOL(_PAGE_E);
|
|
|
|
unsigned long _PAGE_CACHE __read_mostly;
|
|
EXPORT_SYMBOL(_PAGE_CACHE);
|
|
|
|
static void prot_init_common(unsigned long page_none,
|
|
unsigned long page_shared,
|
|
unsigned long page_copy,
|
|
unsigned long page_readonly,
|
|
unsigned long page_exec_bit)
|
|
{
|
|
PAGE_COPY = __pgprot(page_copy);
|
|
PAGE_SHARED = __pgprot(page_shared);
|
|
|
|
protection_map[0x0] = __pgprot(page_none);
|
|
protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
|
|
protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
|
|
protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
|
|
protection_map[0x4] = __pgprot(page_readonly);
|
|
protection_map[0x5] = __pgprot(page_readonly);
|
|
protection_map[0x6] = __pgprot(page_copy);
|
|
protection_map[0x7] = __pgprot(page_copy);
|
|
protection_map[0x8] = __pgprot(page_none);
|
|
protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
|
|
protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
|
|
protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
|
|
protection_map[0xc] = __pgprot(page_readonly);
|
|
protection_map[0xd] = __pgprot(page_readonly);
|
|
protection_map[0xe] = __pgprot(page_shared);
|
|
protection_map[0xf] = __pgprot(page_shared);
|
|
}
|
|
|
|
static void __init sun4u_pgprot_init(void)
|
|
{
|
|
unsigned long page_none, page_shared, page_copy, page_readonly;
|
|
unsigned long page_exec_bit;
|
|
|
|
PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
|
|
_PAGE_CACHE_4U | _PAGE_P_4U |
|
|
__ACCESS_BITS_4U | __DIRTY_BITS_4U |
|
|
_PAGE_EXEC_4U);
|
|
PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
|
|
_PAGE_CACHE_4U | _PAGE_P_4U |
|
|
__ACCESS_BITS_4U | __DIRTY_BITS_4U |
|
|
_PAGE_EXEC_4U | _PAGE_L_4U);
|
|
PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
|
|
|
|
_PAGE_IE = _PAGE_IE_4U;
|
|
_PAGE_E = _PAGE_E_4U;
|
|
_PAGE_CACHE = _PAGE_CACHE_4U;
|
|
|
|
pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
|
|
__ACCESS_BITS_4U | _PAGE_E_4U);
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
|
|
0xfffff80000000000;
|
|
#else
|
|
kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
|
|
0xfffff80000000000;
|
|
#endif
|
|
kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
|
|
_PAGE_P_4U | _PAGE_W_4U);
|
|
|
|
/* XXX Should use 256MB on Panther. XXX */
|
|
kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
|
|
|
|
_PAGE_SZBITS = _PAGE_SZBITS_4U;
|
|
_PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
|
|
_PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
|
|
_PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
|
|
|
|
|
|
page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
|
|
page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
|
|
__ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
|
|
page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
|
|
__ACCESS_BITS_4U | _PAGE_EXEC_4U);
|
|
page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
|
|
__ACCESS_BITS_4U | _PAGE_EXEC_4U);
|
|
|
|
page_exec_bit = _PAGE_EXEC_4U;
|
|
|
|
prot_init_common(page_none, page_shared, page_copy, page_readonly,
|
|
page_exec_bit);
|
|
}
|
|
|
|
static void __init sun4v_pgprot_init(void)
|
|
{
|
|
unsigned long page_none, page_shared, page_copy, page_readonly;
|
|
unsigned long page_exec_bit;
|
|
|
|
PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
|
|
_PAGE_CACHE_4V | _PAGE_P_4V |
|
|
__ACCESS_BITS_4V | __DIRTY_BITS_4V |
|
|
_PAGE_EXEC_4V);
|
|
PAGE_KERNEL_LOCKED = PAGE_KERNEL;
|
|
PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
|
|
|
|
_PAGE_IE = _PAGE_IE_4V;
|
|
_PAGE_E = _PAGE_E_4V;
|
|
_PAGE_CACHE = _PAGE_CACHE_4V;
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
|
|
0xfffff80000000000;
|
|
#else
|
|
kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
|
|
0xfffff80000000000;
|
|
#endif
|
|
kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
|
|
_PAGE_P_4V | _PAGE_W_4V);
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
|
|
0xfffff80000000000;
|
|
#else
|
|
kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
|
|
0xfffff80000000000;
|
|
#endif
|
|
kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
|
|
_PAGE_P_4V | _PAGE_W_4V);
|
|
|
|
pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
|
|
__ACCESS_BITS_4V | _PAGE_E_4V);
|
|
|
|
_PAGE_SZBITS = _PAGE_SZBITS_4V;
|
|
_PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
|
|
_PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
|
|
_PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
|
|
_PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
|
|
|
|
page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
|
|
page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
|
|
__ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
|
|
page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
|
|
__ACCESS_BITS_4V | _PAGE_EXEC_4V);
|
|
page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
|
|
__ACCESS_BITS_4V | _PAGE_EXEC_4V);
|
|
|
|
page_exec_bit = _PAGE_EXEC_4V;
|
|
|
|
prot_init_common(page_none, page_shared, page_copy, page_readonly,
|
|
page_exec_bit);
|
|
}
|
|
|
|
unsigned long pte_sz_bits(unsigned long sz)
|
|
{
|
|
if (tlb_type == hypervisor) {
|
|
switch (sz) {
|
|
case 8 * 1024:
|
|
default:
|
|
return _PAGE_SZ8K_4V;
|
|
case 64 * 1024:
|
|
return _PAGE_SZ64K_4V;
|
|
case 512 * 1024:
|
|
return _PAGE_SZ512K_4V;
|
|
case 4 * 1024 * 1024:
|
|
return _PAGE_SZ4MB_4V;
|
|
};
|
|
} else {
|
|
switch (sz) {
|
|
case 8 * 1024:
|
|
default:
|
|
return _PAGE_SZ8K_4U;
|
|
case 64 * 1024:
|
|
return _PAGE_SZ64K_4U;
|
|
case 512 * 1024:
|
|
return _PAGE_SZ512K_4U;
|
|
case 4 * 1024 * 1024:
|
|
return _PAGE_SZ4MB_4U;
|
|
};
|
|
}
|
|
}
|
|
|
|
pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
|
|
{
|
|
pte_t pte;
|
|
|
|
pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
|
|
pte_val(pte) |= (((unsigned long)space) << 32);
|
|
pte_val(pte) |= pte_sz_bits(page_size);
|
|
|
|
return pte;
|
|
}
|
|
|
|
static unsigned long kern_large_tte(unsigned long paddr)
|
|
{
|
|
unsigned long val;
|
|
|
|
val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
|
|
_PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
|
|
_PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
|
|
if (tlb_type == hypervisor)
|
|
val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
|
|
_PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
|
|
_PAGE_EXEC_4V | _PAGE_W_4V);
|
|
|
|
return val | paddr;
|
|
}
|
|
|
|
/* If not locked, zap it. */
|
|
void __flush_tlb_all(void)
|
|
{
|
|
unsigned long pstate;
|
|
int i;
|
|
|
|
__asm__ __volatile__("flushw\n\t"
|
|
"rdpr %%pstate, %0\n\t"
|
|
"wrpr %0, %1, %%pstate"
|
|
: "=r" (pstate)
|
|
: "i" (PSTATE_IE));
|
|
if (tlb_type == spitfire) {
|
|
for (i = 0; i < 64; i++) {
|
|
/* Spitfire Errata #32 workaround */
|
|
/* NOTE: Always runs on spitfire, so no
|
|
* cheetah+ page size encodings.
|
|
*/
|
|
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
|
|
"flush %%g6"
|
|
: /* No outputs */
|
|
: "r" (0),
|
|
"r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
|
|
|
|
if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
|
|
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
|
"membar #Sync"
|
|
: /* no outputs */
|
|
: "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
|
|
spitfire_put_dtlb_data(i, 0x0UL);
|
|
}
|
|
|
|
/* Spitfire Errata #32 workaround */
|
|
/* NOTE: Always runs on spitfire, so no
|
|
* cheetah+ page size encodings.
|
|
*/
|
|
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
|
|
"flush %%g6"
|
|
: /* No outputs */
|
|
: "r" (0),
|
|
"r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
|
|
|
|
if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
|
|
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
|
|
"membar #Sync"
|
|
: /* no outputs */
|
|
: "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
|
|
spitfire_put_itlb_data(i, 0x0UL);
|
|
}
|
|
}
|
|
} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
|
|
cheetah_flush_dtlb_all();
|
|
cheetah_flush_itlb_all();
|
|
}
|
|
__asm__ __volatile__("wrpr %0, 0, %%pstate"
|
|
: : "r" (pstate));
|
|
}
|
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG
|
|
|
|
void online_page(struct page *page)
|
|
{
|
|
ClearPageReserved(page);
|
|
init_page_count(page);
|
|
__free_page(page);
|
|
totalram_pages++;
|
|
num_physpages++;
|
|
}
|
|
|
|
int remove_memory(u64 start, u64 size)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
#endif /* CONFIG_MEMORY_HOTPLUG */
|