975 lines
26 KiB
C
975 lines
26 KiB
C
/*
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* arch/sh/kernel/traps_64.c
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2003, 2004 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/interrupt.h>
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#include <linux/sysctl.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/atomic.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#undef DEBUG_EXCEPTION
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#ifdef DEBUG_EXCEPTION
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/* implemented in ../lib/dbg.c */
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extern void show_excp_regs(char *fname, int trapnr, int signr,
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struct pt_regs *regs);
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#else
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#define show_excp_regs(a, b, c, d)
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#endif
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static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
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unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
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#define DO_ERROR(trapnr, signr, str, name, tsk) \
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asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
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{ \
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do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
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}
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spinlock_t die_lock;
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void die(const char * str, struct pt_regs * regs, long err)
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{
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console_verbose();
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spin_lock_irq(&die_lock);
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printk("%s: %lx\n", str, (err & 0xffffff));
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show_regs(regs);
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spin_unlock_irq(&die_lock);
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do_exit(SIGSEGV);
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}
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static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
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{
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if (!user_mode(regs))
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die(str, regs, err);
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}
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static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
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{
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if (!user_mode(regs)) {
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const struct exception_table_entry *fixup;
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fixup = search_exception_tables(regs->pc);
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if (fixup) {
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regs->pc = fixup->fixup;
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return;
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}
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die(str, regs, err);
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}
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}
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DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
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DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
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/* Implement misaligned load/store handling for kernel (and optionally for user
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mode too). Limitation : only SHmedia mode code is handled - there is no
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handling at all for misaligned accesses occurring in SHcompact code yet. */
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static int misaligned_fixup(struct pt_regs *regs);
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asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
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{
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if (misaligned_fixup(regs) < 0) {
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do_unhandled_exception(7, SIGSEGV, "address error(load)",
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"do_address_error_load",
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error_code, regs, current);
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}
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return;
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}
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asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
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{
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if (misaligned_fixup(regs) < 0) {
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do_unhandled_exception(8, SIGSEGV, "address error(store)",
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"do_address_error_store",
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error_code, regs, current);
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}
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return;
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}
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#if defined(CONFIG_SH64_ID2815_WORKAROUND)
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#define OPCODE_INVALID 0
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#define OPCODE_USER_VALID 1
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#define OPCODE_PRIV_VALID 2
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/* getcon/putcon - requires checking which control register is referenced. */
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#define OPCODE_CTRL_REG 3
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/* Table of valid opcodes for SHmedia mode.
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Form a 10-bit value by concatenating the major/minor opcodes i.e.
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opcode[31:26,20:16]. The 6 MSBs of this value index into the following
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array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
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LSBs==4'b0000 etc). */
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static unsigned long shmedia_opcode_table[64] = {
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0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
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0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
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0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
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0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
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0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
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0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
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0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
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0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
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};
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void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
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{
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/* Workaround SH5-101 cut2 silicon defect #2815 :
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in some situations, inter-mode branches from SHcompact -> SHmedia
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which should take ITLBMISS or EXECPROT exceptions at the target
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falsely take RESINST at the target instead. */
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unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
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unsigned long pc, aligned_pc;
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int get_user_error;
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int trapnr = 12;
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int signr = SIGILL;
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char *exception_name = "reserved_instruction";
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pc = regs->pc;
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if ((pc & 3) == 1) {
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/* SHmedia : check for defect. This requires executable vmas
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to be readable too. */
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aligned_pc = pc & ~3;
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if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
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get_user_error = -EFAULT;
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} else {
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get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
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}
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if (get_user_error >= 0) {
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unsigned long index, shift;
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unsigned long major, minor, combined;
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unsigned long reserved_field;
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reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
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major = (opcode >> 26) & 0x3f;
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minor = (opcode >> 16) & 0xf;
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combined = (major << 4) | minor;
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index = major;
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shift = minor << 1;
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if (reserved_field == 0) {
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int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
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switch (opcode_state) {
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case OPCODE_INVALID:
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/* Trap. */
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break;
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case OPCODE_USER_VALID:
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/* Restart the instruction : the branch to the instruction will now be from an RTE
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not from SHcompact so the silicon defect won't be triggered. */
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return;
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case OPCODE_PRIV_VALID:
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if (!user_mode(regs)) {
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/* Should only ever get here if a module has
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SHcompact code inside it. If so, the same fix up is needed. */
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return; /* same reason */
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}
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/* Otherwise, user mode trying to execute a privileged instruction -
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fall through to trap. */
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break;
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case OPCODE_CTRL_REG:
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/* If in privileged mode, return as above. */
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if (!user_mode(regs)) return;
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/* In user mode ... */
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if (combined == 0x9f) { /* GETCON */
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unsigned long regno = (opcode >> 20) & 0x3f;
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if (regno >= 62) {
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return;
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}
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/* Otherwise, reserved or privileged control register, => trap */
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} else if (combined == 0x1bf) { /* PUTCON */
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unsigned long regno = (opcode >> 4) & 0x3f;
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if (regno >= 62) {
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return;
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}
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/* Otherwise, reserved or privileged control register, => trap */
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} else {
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/* Trap */
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}
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break;
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default:
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/* Fall through to trap. */
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break;
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}
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}
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/* fall through to normal resinst processing */
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} else {
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/* Error trying to read opcode. This typically means a
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real fault, not a RESINST any more. So change the
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codes. */
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trapnr = 87;
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exception_name = "address error (exec)";
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signr = SIGSEGV;
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}
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}
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do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
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}
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#else /* CONFIG_SH64_ID2815_WORKAROUND */
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/* If the workaround isn't needed, this is just a straightforward reserved
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instruction */
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DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
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#endif /* CONFIG_SH64_ID2815_WORKAROUND */
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/* Called with interrupts disabled */
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asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
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{
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show_excp_regs(__FUNCTION__, -1, -1, regs);
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die_if_kernel("exception", regs, ex);
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}
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int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
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{
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/* Syscall debug */
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printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
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die_if_kernel("unknown trapa", regs, scId);
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return -ENOSYS;
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}
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void show_stack(struct task_struct *tsk, unsigned long *sp)
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{
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#ifdef CONFIG_KALLSYMS
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extern void sh64_unwind(struct pt_regs *regs);
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struct pt_regs *regs;
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regs = tsk ? tsk->thread.kregs : NULL;
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sh64_unwind(regs);
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#else
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printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
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#endif
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}
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void show_task(unsigned long *sp)
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{
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show_stack(NULL, sp);
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}
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void dump_stack(void)
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{
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show_task(NULL);
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}
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/* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
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EXPORT_SYMBOL(dump_stack);
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static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
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unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
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{
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show_excp_regs(fn_name, trapnr, signr, regs);
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tsk->thread.error_code = error_code;
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tsk->thread.trap_no = trapnr;
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if (user_mode(regs))
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force_sig(signr, tsk);
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die_if_no_fixup(str, regs, error_code);
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}
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static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
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{
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int get_user_error;
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unsigned long aligned_pc;
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unsigned long opcode;
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if ((pc & 3) == 1) {
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/* SHmedia */
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aligned_pc = pc & ~3;
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if (from_user_mode) {
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if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
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get_user_error = -EFAULT;
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} else {
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get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
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*result_opcode = opcode;
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}
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return get_user_error;
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} else {
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/* If the fault was in the kernel, we can either read
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* this directly, or if not, we fault.
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*/
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*result_opcode = *(unsigned long *) aligned_pc;
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return 0;
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}
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} else if ((pc & 1) == 0) {
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/* SHcompact */
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/* TODO : provide handling for this. We don't really support
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user-mode SHcompact yet, and for a kernel fault, this would
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have to come from a module built for SHcompact. */
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return -EFAULT;
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} else {
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/* misaligned */
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return -EFAULT;
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}
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}
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static int address_is_sign_extended(__u64 a)
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{
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__u64 b;
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#if (NEFF == 32)
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b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
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return (b == a) ? 1 : 0;
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#else
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#error "Sign extend check only works for NEFF==32"
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#endif
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}
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static int generate_and_check_address(struct pt_regs *regs,
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__u32 opcode,
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int displacement_not_indexed,
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int width_shift,
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__u64 *address)
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{
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/* return -1 for fault, 0 for OK */
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__u64 base_address, addr;
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int basereg;
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basereg = (opcode >> 20) & 0x3f;
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base_address = regs->regs[basereg];
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if (displacement_not_indexed) {
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__s64 displacement;
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displacement = (opcode >> 10) & 0x3ff;
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displacement = ((displacement << 54) >> 54); /* sign extend */
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addr = (__u64)((__s64)base_address + (displacement << width_shift));
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} else {
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__u64 offset;
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int offsetreg;
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offsetreg = (opcode >> 10) & 0x3f;
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offset = regs->regs[offsetreg];
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addr = base_address + offset;
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}
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/* Check sign extended */
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if (!address_is_sign_extended(addr)) {
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return -1;
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}
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#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
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/* Check accessible. For misaligned access in the kernel, assume the
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address is always accessible (and if not, just fault when the
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load/store gets done.) */
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if (user_mode(regs)) {
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if (addr >= TASK_SIZE) {
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return -1;
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}
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/* Do access_ok check later - it depends on whether it's a load or a store. */
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}
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#endif
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*address = addr;
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return 0;
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}
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/* Default value as for sh */
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#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
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static int user_mode_unaligned_fixup_count = 10;
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static int user_mode_unaligned_fixup_enable = 1;
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#endif
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static int kernel_mode_unaligned_fixup_count = 32;
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static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
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{
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unsigned short x;
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unsigned char *p, *q;
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p = (unsigned char *) (int) address;
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q = (unsigned char *) &x;
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q[0] = p[0];
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q[1] = p[1];
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if (do_sign_extend) {
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*result = (__u64)(__s64) *(short *) &x;
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} else {
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*result = (__u64) x;
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}
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}
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static void misaligned_kernel_word_store(__u64 address, __u64 value)
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{
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unsigned short x;
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unsigned char *p, *q;
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p = (unsigned char *) (int) address;
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q = (unsigned char *) &x;
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x = (__u16) value;
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p[0] = q[0];
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p[1] = q[1];
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}
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|
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static int misaligned_load(struct pt_regs *regs,
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__u32 opcode,
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int displacement_not_indexed,
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int width_shift,
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int do_sign_extend)
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{
|
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/* Return -1 for a fault, 0 for OK */
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int error;
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int destreg;
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__u64 address;
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error = generate_and_check_address(regs, opcode,
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displacement_not_indexed, width_shift, &address);
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if (error < 0) {
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return error;
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}
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destreg = (opcode >> 4) & 0x3f;
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#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
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if (user_mode(regs)) {
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__u64 buffer;
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|
|
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if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
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return -1;
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}
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if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
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return -1; /* fault */
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}
|
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switch (width_shift) {
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case 1:
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if (do_sign_extend) {
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regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
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} else {
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regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
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}
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break;
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case 2:
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regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
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break;
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case 3:
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regs->regs[destreg] = buffer;
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
|
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} else
|
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#endif
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{
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/* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
|
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__u64 lo, hi;
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|
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switch (width_shift) {
|
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case 1:
|
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misaligned_kernel_word_load(address, do_sign_extend, ®s->regs[destreg]);
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break;
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case 2:
|
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asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
|
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asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
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regs->regs[destreg] = lo | hi;
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break;
|
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case 3:
|
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asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
|
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asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
|
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regs->regs[destreg] = lo | hi;
|
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break;
|
|
|
|
default:
|
|
printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
|
|
width_shift, (unsigned long) regs->pc);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static int misaligned_store(struct pt_regs *regs,
|
|
__u32 opcode,
|
|
int displacement_not_indexed,
|
|
int width_shift)
|
|
{
|
|
/* Return -1 for a fault, 0 for OK */
|
|
int error;
|
|
int srcreg;
|
|
__u64 address;
|
|
|
|
error = generate_and_check_address(regs, opcode,
|
|
displacement_not_indexed, width_shift, &address);
|
|
if (error < 0) {
|
|
return error;
|
|
}
|
|
|
|
srcreg = (opcode >> 4) & 0x3f;
|
|
#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
if (user_mode(regs)) {
|
|
__u64 buffer;
|
|
|
|
if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
|
|
return -1;
|
|
}
|
|
|
|
switch (width_shift) {
|
|
case 1:
|
|
*(__u16 *) &buffer = (__u16) regs->regs[srcreg];
|
|
break;
|
|
case 2:
|
|
*(__u32 *) &buffer = (__u32) regs->regs[srcreg];
|
|
break;
|
|
case 3:
|
|
buffer = regs->regs[srcreg];
|
|
break;
|
|
default:
|
|
printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
|
|
width_shift, (unsigned long) regs->pc);
|
|
break;
|
|
}
|
|
|
|
if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
|
|
return -1; /* fault */
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
/* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
|
|
__u64 val = regs->regs[srcreg];
|
|
|
|
switch (width_shift) {
|
|
case 1:
|
|
misaligned_kernel_word_store(address, val);
|
|
break;
|
|
case 2:
|
|
asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
|
|
asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
|
|
break;
|
|
case 3:
|
|
asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
|
|
asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
|
|
break;
|
|
|
|
default:
|
|
printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
|
|
width_shift, (unsigned long) regs->pc);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
/* Never need to fix up misaligned FPU accesses within the kernel since that's a real
|
|
error. */
|
|
static int misaligned_fpu_load(struct pt_regs *regs,
|
|
__u32 opcode,
|
|
int displacement_not_indexed,
|
|
int width_shift,
|
|
int do_paired_load)
|
|
{
|
|
/* Return -1 for a fault, 0 for OK */
|
|
int error;
|
|
int destreg;
|
|
__u64 address;
|
|
|
|
error = generate_and_check_address(regs, opcode,
|
|
displacement_not_indexed, width_shift, &address);
|
|
if (error < 0) {
|
|
return error;
|
|
}
|
|
|
|
destreg = (opcode >> 4) & 0x3f;
|
|
if (user_mode(regs)) {
|
|
__u64 buffer;
|
|
__u32 buflo, bufhi;
|
|
|
|
if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
|
|
return -1;
|
|
}
|
|
|
|
if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
|
|
return -1; /* fault */
|
|
}
|
|
/* 'current' may be the current owner of the FPU state, so
|
|
context switch the registers into memory so they can be
|
|
indexed by register number. */
|
|
if (last_task_used_math == current) {
|
|
enable_fpu();
|
|
save_fpu(current, regs);
|
|
disable_fpu();
|
|
last_task_used_math = NULL;
|
|
regs->sr |= SR_FD;
|
|
}
|
|
|
|
buflo = *(__u32*) &buffer;
|
|
bufhi = *(1 + (__u32*) &buffer);
|
|
|
|
switch (width_shift) {
|
|
case 2:
|
|
current->thread.fpu.hard.fp_regs[destreg] = buflo;
|
|
break;
|
|
case 3:
|
|
if (do_paired_load) {
|
|
current->thread.fpu.hard.fp_regs[destreg] = buflo;
|
|
current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
|
|
} else {
|
|
#if defined(CONFIG_LITTLE_ENDIAN)
|
|
current->thread.fpu.hard.fp_regs[destreg] = bufhi;
|
|
current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
|
|
#else
|
|
current->thread.fpu.hard.fp_regs[destreg] = buflo;
|
|
current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
|
|
#endif
|
|
}
|
|
break;
|
|
default:
|
|
printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
|
|
width_shift, (unsigned long) regs->pc);
|
|
break;
|
|
}
|
|
return 0;
|
|
} else {
|
|
die ("Misaligned FPU load inside kernel", regs, 0);
|
|
return -1;
|
|
}
|
|
|
|
|
|
}
|
|
|
|
static int misaligned_fpu_store(struct pt_regs *regs,
|
|
__u32 opcode,
|
|
int displacement_not_indexed,
|
|
int width_shift,
|
|
int do_paired_load)
|
|
{
|
|
/* Return -1 for a fault, 0 for OK */
|
|
int error;
|
|
int srcreg;
|
|
__u64 address;
|
|
|
|
error = generate_and_check_address(regs, opcode,
|
|
displacement_not_indexed, width_shift, &address);
|
|
if (error < 0) {
|
|
return error;
|
|
}
|
|
|
|
srcreg = (opcode >> 4) & 0x3f;
|
|
if (user_mode(regs)) {
|
|
__u64 buffer;
|
|
/* Initialise these to NaNs. */
|
|
__u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
|
|
|
|
if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
|
|
return -1;
|
|
}
|
|
|
|
/* 'current' may be the current owner of the FPU state, so
|
|
context switch the registers into memory so they can be
|
|
indexed by register number. */
|
|
if (last_task_used_math == current) {
|
|
enable_fpu();
|
|
save_fpu(current, regs);
|
|
disable_fpu();
|
|
last_task_used_math = NULL;
|
|
regs->sr |= SR_FD;
|
|
}
|
|
|
|
switch (width_shift) {
|
|
case 2:
|
|
buflo = current->thread.fpu.hard.fp_regs[srcreg];
|
|
break;
|
|
case 3:
|
|
if (do_paired_load) {
|
|
buflo = current->thread.fpu.hard.fp_regs[srcreg];
|
|
bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
|
|
} else {
|
|
#if defined(CONFIG_LITTLE_ENDIAN)
|
|
bufhi = current->thread.fpu.hard.fp_regs[srcreg];
|
|
buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
|
|
#else
|
|
buflo = current->thread.fpu.hard.fp_regs[srcreg];
|
|
bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
|
|
#endif
|
|
}
|
|
break;
|
|
default:
|
|
printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
|
|
width_shift, (unsigned long) regs->pc);
|
|
break;
|
|
}
|
|
|
|
*(__u32*) &buffer = buflo;
|
|
*(1 + (__u32*) &buffer) = bufhi;
|
|
if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
|
|
return -1; /* fault */
|
|
}
|
|
return 0;
|
|
} else {
|
|
die ("Misaligned FPU load inside kernel", regs, 0);
|
|
return -1;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static int misaligned_fixup(struct pt_regs *regs)
|
|
{
|
|
unsigned long opcode;
|
|
int error;
|
|
int major, minor;
|
|
|
|
#if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
/* Never fixup user mode misaligned accesses without this option enabled. */
|
|
return -1;
|
|
#else
|
|
if (!user_mode_unaligned_fixup_enable) return -1;
|
|
#endif
|
|
|
|
error = read_opcode(regs->pc, &opcode, user_mode(regs));
|
|
if (error < 0) {
|
|
return error;
|
|
}
|
|
major = (opcode >> 26) & 0x3f;
|
|
minor = (opcode >> 16) & 0xf;
|
|
|
|
#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
|
|
--user_mode_unaligned_fixup_count;
|
|
/* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
|
|
printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
|
|
current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
|
|
} else
|
|
#endif
|
|
if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
|
|
--kernel_mode_unaligned_fixup_count;
|
|
if (in_interrupt()) {
|
|
printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
|
|
(__u32)regs->pc, opcode);
|
|
} else {
|
|
printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
|
|
current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
|
|
}
|
|
}
|
|
|
|
|
|
switch (major) {
|
|
case (0x84>>2): /* LD.W */
|
|
error = misaligned_load(regs, opcode, 1, 1, 1);
|
|
break;
|
|
case (0xb0>>2): /* LD.UW */
|
|
error = misaligned_load(regs, opcode, 1, 1, 0);
|
|
break;
|
|
case (0x88>>2): /* LD.L */
|
|
error = misaligned_load(regs, opcode, 1, 2, 1);
|
|
break;
|
|
case (0x8c>>2): /* LD.Q */
|
|
error = misaligned_load(regs, opcode, 1, 3, 0);
|
|
break;
|
|
|
|
case (0xa4>>2): /* ST.W */
|
|
error = misaligned_store(regs, opcode, 1, 1);
|
|
break;
|
|
case (0xa8>>2): /* ST.L */
|
|
error = misaligned_store(regs, opcode, 1, 2);
|
|
break;
|
|
case (0xac>>2): /* ST.Q */
|
|
error = misaligned_store(regs, opcode, 1, 3);
|
|
break;
|
|
|
|
case (0x40>>2): /* indexed loads */
|
|
switch (minor) {
|
|
case 0x1: /* LDX.W */
|
|
error = misaligned_load(regs, opcode, 0, 1, 1);
|
|
break;
|
|
case 0x5: /* LDX.UW */
|
|
error = misaligned_load(regs, opcode, 0, 1, 0);
|
|
break;
|
|
case 0x2: /* LDX.L */
|
|
error = misaligned_load(regs, opcode, 0, 2, 1);
|
|
break;
|
|
case 0x3: /* LDX.Q */
|
|
error = misaligned_load(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case (0x60>>2): /* indexed stores */
|
|
switch (minor) {
|
|
case 0x1: /* STX.W */
|
|
error = misaligned_store(regs, opcode, 0, 1);
|
|
break;
|
|
case 0x2: /* STX.L */
|
|
error = misaligned_store(regs, opcode, 0, 2);
|
|
break;
|
|
case 0x3: /* STX.Q */
|
|
error = misaligned_store(regs, opcode, 0, 3);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
case (0x94>>2): /* FLD.S */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
|
|
break;
|
|
case (0x98>>2): /* FLD.P */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
|
|
break;
|
|
case (0x9c>>2): /* FLD.D */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
|
|
break;
|
|
case (0x1c>>2): /* floating indexed loads */
|
|
switch (minor) {
|
|
case 0x8: /* FLDX.S */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
|
|
break;
|
|
case 0xd: /* FLDX.P */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
|
|
break;
|
|
case 0x9: /* FLDX.D */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
case (0xb4>>2): /* FLD.S */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
|
|
break;
|
|
case (0xb8>>2): /* FLD.P */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
|
|
break;
|
|
case (0xbc>>2): /* FLD.D */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
|
|
break;
|
|
case (0x3c>>2): /* floating indexed stores */
|
|
switch (minor) {
|
|
case 0x8: /* FSTX.S */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
|
|
break;
|
|
case 0xd: /* FSTX.P */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
|
|
break;
|
|
case 0x9: /* FSTX.D */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
/* Fault */
|
|
error = -1;
|
|
break;
|
|
}
|
|
|
|
if (error < 0) {
|
|
return error;
|
|
} else {
|
|
regs->pc += 4; /* Skip the instruction that's just been emulated */
|
|
return 0;
|
|
}
|
|
|
|
}
|
|
|
|
static ctl_table unaligned_table[] = {
|
|
{
|
|
.ctl_name = CTL_UNNUMBERED,
|
|
.procname = "kernel_reports",
|
|
.data = &kernel_mode_unaligned_fixup_count,
|
|
.maxlen = sizeof(int),
|
|
.mode = 0644,
|
|
.proc_handler = &proc_dointvec
|
|
},
|
|
#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
|
|
{
|
|
.ctl_name = CTL_UNNUMBERED,
|
|
.procname = "user_reports",
|
|
.data = &user_mode_unaligned_fixup_count,
|
|
.maxlen = sizeof(int),
|
|
.mode = 0644,
|
|
.proc_handler = &proc_dointvec
|
|
},
|
|
{
|
|
.ctl_name = CTL_UNNUMBERED,
|
|
.procname = "user_enable",
|
|
.data = &user_mode_unaligned_fixup_enable,
|
|
.maxlen = sizeof(int),
|
|
.mode = 0644,
|
|
.proc_handler = &proc_dointvec},
|
|
#endif
|
|
{}
|
|
};
|
|
|
|
static ctl_table unaligned_root[] = {
|
|
{
|
|
.ctl_name = CTL_UNNUMBERED,
|
|
.procname = "unaligned_fixup",
|
|
.mode = 0555,
|
|
unaligned_table
|
|
},
|
|
{}
|
|
};
|
|
|
|
static ctl_table sh64_root[] = {
|
|
{
|
|
.ctl_name = CTL_UNNUMBERED,
|
|
.procname = "sh64",
|
|
.mode = 0555,
|
|
.child = unaligned_root
|
|
},
|
|
{}
|
|
};
|
|
static struct ctl_table_header *sysctl_header;
|
|
static int __init init_sysctl(void)
|
|
{
|
|
sysctl_header = register_sysctl_table(sh64_root);
|
|
return 0;
|
|
}
|
|
|
|
__initcall(init_sysctl);
|
|
|
|
|
|
asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
|
|
{
|
|
u64 peek_real_address_q(u64 addr);
|
|
u64 poke_real_address_q(u64 addr, u64 val);
|
|
unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
|
|
unsigned long long exp_cause;
|
|
/* It's not worth ioremapping the debug module registers for the amount
|
|
of access we make to them - just go direct to their physical
|
|
addresses. */
|
|
exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
|
|
if (exp_cause & ~4) {
|
|
printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
|
|
(unsigned long)(exp_cause & 0xffffffff));
|
|
}
|
|
show_state();
|
|
/* Clear all DEBUGINT causes */
|
|
poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
|
|
}
|