df0c382436
Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs to be cleared after PMIC IRQ occured. Now append the clear operation in irq chip handler. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
/*
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* linux/arch/arm/mach-mmp/mmp2.c
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*
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* code name MMP2
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*
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* Copyright (C) 2009 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/addr-map.h>
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#include <mach/regs-apbc.h>
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#include <mach/regs-apmu.h>
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#include <mach/cputype.h>
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#include <mach/irqs.h>
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#include <mach/mfp.h>
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#include <mach/gpio.h>
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#include <mach/devices.h>
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#include "common.h"
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#include "clock.h"
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#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
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#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
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static struct mfp_addr_map mmp2_addr_map[] __initdata = {
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MFP_ADDR(PMIC_INT, 0x2c4),
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MFP_ADDR_END,
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};
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void mmp2_clear_pmic_int(void)
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{
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unsigned long mfpr_pmic, data;
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mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
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data = __raw_readl(mfpr_pmic);
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__raw_writel(data | (1 << 6), mfpr_pmic);
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__raw_writel(data, mfpr_pmic);
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}
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static void __init mmp2_init_gpio(void)
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{
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int i;
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/* enable GPIO clock */
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__raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
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/* unmask GPIO edge detection for all 6 banks -- APMASKx */
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for (i = 0; i < 6; i++)
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__raw_writel(0xffffffff, APMASK(i));
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pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL);
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}
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void __init mmp2_init_irq(void)
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{
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mmp2_init_icu();
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mmp2_init_gpio();
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}
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/* APB peripheral clocks */
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static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
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static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
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static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
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static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
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static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
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static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
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static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
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static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
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static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
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static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
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static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
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static APMU_CLK(nand, NAND, 0xbf, 100000000);
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static struct clk_lookup mmp2_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
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INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
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INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
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INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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};
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static int __init mmp2_init(void)
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{
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if (cpu_is_mmp2()) {
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_addr(mmp2_addr_map);
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clks_register(ARRAY_AND_SIZE(mmp2_clkregs));
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}
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return 0;
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}
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postcore_initcall(mmp2_init);
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/* on-chip devices */
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MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
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MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
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MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
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MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
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MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
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MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
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MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
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MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
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MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
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MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
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MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
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