157 lines
4 KiB
C
157 lines
4 KiB
C
/*
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* Toshiba RBTX4938 specific interrupt handlers
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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/*
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* MIPS_CPU_IRQ_BASE+00 Software 0
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* MIPS_CPU_IRQ_BASE+01 Software 1
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* MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
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* MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
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* MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
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* MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
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* MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
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* MIPS_CPU_IRQ_BASE+07 CPU TIMER
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*
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* TXX9_IRQ_BASE+00
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* TXX9_IRQ_BASE+01
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* TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
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* TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
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* TXX9_IRQ_BASE+04
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* TXX9_IRQ_BASE+05 TX4938 ETH1
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* TXX9_IRQ_BASE+06 TX4938 ETH0
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* TXX9_IRQ_BASE+07
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* TXX9_IRQ_BASE+08 TX4938 SIO 0
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* TXX9_IRQ_BASE+09 TX4938 SIO 1
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* TXX9_IRQ_BASE+10 TX4938 DMA0
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* TXX9_IRQ_BASE+11 TX4938 DMA1
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* TXX9_IRQ_BASE+12 TX4938 DMA2
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* TXX9_IRQ_BASE+13 TX4938 DMA3
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* TXX9_IRQ_BASE+14
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* TXX9_IRQ_BASE+15
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* TXX9_IRQ_BASE+16 TX4938 PCIC
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* TXX9_IRQ_BASE+17 TX4938 TMR0
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* TXX9_IRQ_BASE+18 TX4938 TMR1
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* TXX9_IRQ_BASE+19 TX4938 TMR2
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* TXX9_IRQ_BASE+20
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* TXX9_IRQ_BASE+21
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* TXX9_IRQ_BASE+22 TX4938 PCIERR
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* TXX9_IRQ_BASE+23
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* TXX9_IRQ_BASE+24
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* TXX9_IRQ_BASE+25
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* TXX9_IRQ_BASE+26
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* TXX9_IRQ_BASE+27
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* TXX9_IRQ_BASE+28
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* TXX9_IRQ_BASE+29
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* TXX9_IRQ_BASE+30
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* TXX9_IRQ_BASE+31 TX4938 SPI
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*
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* RBTX4938_IRQ_IOC+00 PCI-D
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* RBTX4938_IRQ_IOC+01 PCI-C
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* RBTX4938_IRQ_IOC+02 PCI-B
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* RBTX4938_IRQ_IOC+03 PCI-A
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* RBTX4938_IRQ_IOC+04 RTC
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* RBTX4938_IRQ_IOC+05 ATA
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* RBTX4938_IRQ_IOC+06 MODEM
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* RBTX4938_IRQ_IOC+07 SWINT
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/rbtx4938.h>
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static int toshiba_rbtx4938_irq_nested(int sw_irq)
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{
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u8 level3;
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level3 = readb(rbtx4938_imstat_addr);
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if (unlikely(!level3))
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return -1;
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/* must use fls so onboard ATA has priority */
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return RBTX4938_IRQ_IOC + __fls8(level3);
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}
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static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
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{
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unsigned char v;
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v = readb(rbtx4938_imask_addr);
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v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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}
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static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
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{
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unsigned char v;
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v = readb(rbtx4938_imask_addr);
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v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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}
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#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
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static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
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.name = TOSHIBA_RBTX4938_IOC_NAME,
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.irq_mask = toshiba_rbtx4938_irq_ioc_disable,
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.irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
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};
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static int rbtx4938_irq_dispatch(int pending)
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{
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int irq;
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if (pending & STATUSF_IP7)
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irq = MIPS_CPU_IRQ_BASE + 7;
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else if (pending & STATUSF_IP2) {
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irq = txx9_irq();
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if (irq == RBTX4938_IRQ_IOCINT)
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irq = toshiba_rbtx4938_irq_nested(irq);
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} else if (pending & STATUSF_IP1)
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irq = MIPS_CPU_IRQ_BASE + 0;
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else if (pending & STATUSF_IP0)
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irq = MIPS_CPU_IRQ_BASE + 1;
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else
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irq = -1;
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return irq;
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}
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static void __init toshiba_rbtx4938_irq_ioc_init(void)
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{
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int i;
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for (i = RBTX4938_IRQ_IOC;
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i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
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irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
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handle_level_irq);
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irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
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}
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void __init rbtx4938_irq_setup(void)
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{
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txx9_irq_dispatch = rbtx4938_irq_dispatch;
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/* Now, interrupt control disabled, */
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/* all IRC interrupts are masked, */
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/* all IRC interrupt mode are Low Active. */
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/* mask all IOC interrupts */
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writeb(0, rbtx4938_imask_addr);
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/* clear SoftInt interrupts */
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writeb(0, rbtx4938_softint_addr);
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tx4938_irq_init();
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toshiba_rbtx4938_irq_ioc_init();
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/* Onboard 10M Ether: High Active */
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irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
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}
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