171bb2f19e
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LANTIQ_H__
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#define _LANTIQ_H__
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#include <linux/irq.h>
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/* generic reg access functions */
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#define ltq_r32(reg) __raw_readl(reg)
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#define ltq_w32(val, reg) __raw_writel(val, reg)
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#define ltq_w32_mask(clear, set, reg) \
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ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
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#define ltq_r8(reg) __raw_readb(reg)
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#define ltq_w8(val, reg) __raw_writeb(val, reg)
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/* register access macros for EBU and CGU */
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#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
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#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
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#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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extern __iomem void *ltq_ebu_membase;
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extern __iomem void *ltq_cgu_membase;
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extern unsigned int ltq_get_cpu_ver(void);
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extern unsigned int ltq_get_soc_type(void);
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/* clock speeds */
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#define CLOCK_60M 60000000
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#define CLOCK_83M 83333333
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#define CLOCK_111M 111111111
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#define CLOCK_133M 133333333
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#define CLOCK_167M 166666667
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#define CLOCK_200M 200000000
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#define CLOCK_266M 266666666
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#define CLOCK_333M 333333333
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#define CLOCK_400M 400000000
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/* spinlock all ebu i/o */
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extern spinlock_t ebu_lock;
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/* some irq helpers */
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extern void ltq_disable_irq(struct irq_data *data);
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extern void ltq_mask_and_ack_irq(struct irq_data *data);
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extern void ltq_enable_irq(struct irq_data *data);
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/* find out what caused the last cpu reset */
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extern int ltq_reset_cause(void);
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#define LTQ_RST_CAUSE_WDTRST 0x20
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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#define LTQ_FLASH_START 0x10000000
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#define LTQ_FLASH_MAX 0x04000000
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#endif
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