5b3b16880f
These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
70 lines
1.5 KiB
ArmAsm
70 lines
1.5 KiB
ArmAsm
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2006 Cavium Networks
|
|
* Cache error handler
|
|
*/
|
|
|
|
#include <asm/asm.h>
|
|
#include <asm/regdef.h>
|
|
#include <asm/mipsregs.h>
|
|
#include <asm/stackframe.h>
|
|
|
|
/*
|
|
* Handle cache error. Indicate to the second level handler whether
|
|
* the exception is recoverable.
|
|
*/
|
|
LEAF(except_vec2_octeon)
|
|
|
|
.set push
|
|
.set mips64r2
|
|
.set noreorder
|
|
.set noat
|
|
|
|
|
|
/* due to an errata we need to read the COP0 CacheErr (Dcache)
|
|
* before any cache/DRAM access */
|
|
|
|
rdhwr k0, $0 /* get core_id */
|
|
PTR_LA k1, cache_err_dcache
|
|
sll k0, k0, 3
|
|
PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
|
|
|
|
dmfc0 k0, CP0_CACHEERR, 1
|
|
sd k0, (k1)
|
|
dmtc0 $0, CP0_CACHEERR, 1
|
|
|
|
/* check whether this is a nested exception */
|
|
mfc0 k1, CP0_STATUS
|
|
andi k1, k1, ST0_EXL
|
|
beqz k1, 1f
|
|
nop
|
|
j cache_parity_error_octeon_non_recoverable
|
|
nop
|
|
|
|
/* exception is recoverable */
|
|
1: j handle_cache_err
|
|
nop
|
|
|
|
.set pop
|
|
END(except_vec2_octeon)
|
|
|
|
/* We need to jump to handle_cache_err so that the previous handler
|
|
* can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
|
|
* space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */
|
|
LEAF(handle_cache_err)
|
|
.set push
|
|
.set noreorder
|
|
.set noat
|
|
|
|
SAVE_ALL
|
|
KMODE
|
|
jal cache_parity_error_octeon_recoverable
|
|
nop
|
|
j ret_from_exception
|
|
nop
|
|
|
|
.set pop
|
|
END(handle_cache_err)
|