5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
1061 lines
29 KiB
C
1061 lines
29 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/io.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/tioce_provider.h>
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/*
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* 1/26/2006
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*
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* WAR for SGI PV 944642. For revA TIOCE, need to use the following recipe
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* (taken from the above PV) before and after accessing tioce internal MMR's
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* to avoid tioce lockups.
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*
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* The recipe as taken from the PV:
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*
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* if(mmr address < 0x45000) {
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* if(mmr address == 0 or 0x80)
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* mmr wrt or read address 0xc0
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* else if(mmr address == 0x148 or 0x200)
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* mmr wrt or read address 0x28
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* else
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* mmr wrt or read address 0x158
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*
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* do desired mmr access (rd or wrt)
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*
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* if(mmr address == 0x100)
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* mmr wrt or read address 0x38
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* mmr wrt or read address 0xb050
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* } else
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* do desired mmr access
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*
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* According to hw, we can use reads instead of writes to the above address
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*
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* Note this WAR can only to be used for accessing internal MMR's in the
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* TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
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* "Local CE Registers and Memories" and "PCI Compatible Config Space" address
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* spaces from table 2-1 of the "CE Programmer's Reference Overview" document.
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*
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* All registers defined in struct tioce will meet that criteria.
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*/
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static void inline
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tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr)
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{
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u64 mmr_base;
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u64 mmr_offset;
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if (kern->ce_common->ce_rev != TIOCE_REV_A)
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return;
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mmr_base = kern->ce_common->ce_pcibus.bs_base;
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mmr_offset = (unsigned long)mmr_addr - mmr_base;
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if (mmr_offset < 0x45000) {
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u64 mmr_war_offset;
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if (mmr_offset == 0 || mmr_offset == 0x80)
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mmr_war_offset = 0xc0;
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else if (mmr_offset == 0x148 || mmr_offset == 0x200)
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mmr_war_offset = 0x28;
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else
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mmr_war_offset = 0x158;
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readq_relaxed((void __iomem *)(mmr_base + mmr_war_offset));
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}
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}
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static void inline
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tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr)
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{
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u64 mmr_base;
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u64 mmr_offset;
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if (kern->ce_common->ce_rev != TIOCE_REV_A)
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return;
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mmr_base = kern->ce_common->ce_pcibus.bs_base;
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mmr_offset = (unsigned long)mmr_addr - mmr_base;
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if (mmr_offset < 0x45000) {
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if (mmr_offset == 0x100)
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readq_relaxed((void __iomem *)(mmr_base + 0x38));
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readq_relaxed((void __iomem *)(mmr_base + 0xb050));
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}
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}
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/* load mmr contents into a variable */
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#define tioce_mmr_load(kern, mmrp, varp) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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*(varp) = readq_relaxed(mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* store variable contents into mmr */
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#define tioce_mmr_store(kern, mmrp, varp) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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writeq(*varp, mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* store immediate value into mmr */
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#define tioce_mmr_storei(kern, mmrp, val) do {\
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tioce_mmr_war_pre(kern, mmrp); \
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writeq(val, mmrp); \
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tioce_mmr_war_post(kern, mmrp); \
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} while (0)
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/* set bits (immediate value) into mmr */
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#define tioce_mmr_seti(kern, mmrp, bits) do {\
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u64 tmp; \
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tioce_mmr_load(kern, mmrp, &tmp); \
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tmp |= (bits); \
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tioce_mmr_store(kern, mmrp, &tmp); \
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} while (0)
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/* clear bits (immediate value) into mmr */
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#define tioce_mmr_clri(kern, mmrp, bits) do { \
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u64 tmp; \
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tioce_mmr_load(kern, mmrp, &tmp); \
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tmp &= ~(bits); \
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tioce_mmr_store(kern, mmrp, &tmp); \
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} while (0)
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/**
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* Bus address ranges for the 5 flavors of TIOCE DMA
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*/
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#define TIOCE_D64_MIN 0x8000000000000000UL
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#define TIOCE_D64_MAX 0xffffffffffffffffUL
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#define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN)
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#define TIOCE_D32_MIN 0x0000000080000000UL
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#define TIOCE_D32_MAX 0x00000000ffffffffUL
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#define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
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#define TIOCE_M32_MIN 0x0000000000000000UL
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#define TIOCE_M32_MAX 0x000000007fffffffUL
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#define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
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#define TIOCE_M40_MIN 0x0000004000000000UL
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#define TIOCE_M40_MAX 0x0000007fffffffffUL
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#define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
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#define TIOCE_M40S_MIN 0x0000008000000000UL
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#define TIOCE_M40S_MAX 0x000000ffffffffffUL
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#define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
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/*
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* ATE manipulation macros.
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*/
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#define ATE_PAGESHIFT(ps) (__ffs(ps))
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#define ATE_PAGEMASK(ps) ((ps)-1)
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#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
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#define ATE_NPAGES(start, len, pagesize) \
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(ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
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#define ATE_VALID(ate) ((ate) & (1UL << 63))
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#define ATE_MAKE(addr, ps, msi) \
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(((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0))
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/*
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* Flavors of ate-based mapping supported by tioce_alloc_map()
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*/
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#define TIOCE_ATE_M32 1
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#define TIOCE_ATE_M40 2
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#define TIOCE_ATE_M40S 3
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#define KB(x) ((u64)(x) << 10)
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#define MB(x) ((u64)(x) << 20)
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#define GB(x) ((u64)(x) << 30)
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/**
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* tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
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* @ct_addr: system coretalk address
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*
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* Map @ct_addr into 64-bit CE bus space. No device context is necessary
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* and no CE mapping are consumed.
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*
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* Bits 53:0 come from the coretalk address. The remaining bits are set as
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* follows:
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*
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* 63 - must be 1 to indicate d64 mode to CE hardware
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* 62 - barrier bit ... controlled with tioce_dma_barrier()
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* 61 - msi bit ... specified through dma_flags
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* 60:54 - reserved, MBZ
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*/
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static u64
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tioce_dma_d64(unsigned long ct_addr, int dma_flags)
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{
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u64 bus_addr;
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bus_addr = ct_addr | (1UL << 63);
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if (dma_flags & SN_DMA_MSI)
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bus_addr |= (1UL << 61);
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return bus_addr;
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}
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/**
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* pcidev_to_tioce - return misc ce related pointers given a pci_dev
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* @pci_dev: pci device context
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* @base: ptr to store struct tioce_mmr * for the CE holding this device
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* @kernel: ptr to store struct tioce_kernel * for the CE holding this device
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* @port: ptr to store the CE port number that this device is on
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*
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* Return pointers to various CE-related structures for the CE upstream of
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* @pci_dev.
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*/
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static inline void
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pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
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struct tioce_kernel **kernel, int *port)
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{
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struct pcidev_info *pcidev_info;
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struct tioce_common *ce_common;
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struct tioce_kernel *ce_kernel;
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pcidev_info = SN_PCIDEV_INFO(pdev);
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ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
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ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
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if (base)
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*base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
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if (kernel)
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*kernel = ce_kernel;
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/*
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* we use port as a zero-based value internally, even though the
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* documentation is 1-based.
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*/
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if (port)
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*port =
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(pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1;
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}
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/**
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* tioce_alloc_map - Given a coretalk address, map it to pcie bus address
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* space using one of the various ATE-based address modes.
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* @ce_kern: tioce context
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* @type: map mode to use
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* @port: 0-based port that the requesting device is downstream of
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* @ct_addr: the coretalk address to map
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* @len: number of bytes to map
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*
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* Given the addressing type, set up various parameters that define the
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* ATE pool to use. Search for a contiguous block of entries to cover the
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* length, and if enough resources exist, fill in the ATEs and construct a
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* tioce_dmamap struct to track the mapping.
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*/
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static u64
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tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
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u64 ct_addr, int len, int dma_flags)
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{
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int i;
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int j;
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int first;
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int last;
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int entries;
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int nates;
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u64 pagesize;
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int msi_capable, msi_wanted;
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u64 *ate_shadow;
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u64 __iomem *ate_reg;
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u64 addr;
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struct tioce __iomem *ce_mmr;
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u64 bus_base;
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struct tioce_dmamap *map;
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ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
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switch (type) {
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case TIOCE_ATE_M32:
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/*
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* The first 64 entries of the ate3240 pool are dedicated to
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* super-page (TIOCE_ATE_M40S) mode.
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*/
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first = 64;
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entries = TIOCE_NUM_M3240_ATES - 64;
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ate_shadow = ce_kern->ce_ate3240_shadow;
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ate_reg = ce_mmr->ce_ure_ate3240;
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pagesize = ce_kern->ce_ate3240_pagesize;
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bus_base = TIOCE_M32_MIN;
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msi_capable = 1;
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break;
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case TIOCE_ATE_M40:
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first = 0;
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entries = TIOCE_NUM_M40_ATES;
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ate_shadow = ce_kern->ce_ate40_shadow;
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ate_reg = ce_mmr->ce_ure_ate40;
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pagesize = MB(64);
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bus_base = TIOCE_M40_MIN;
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msi_capable = 0;
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break;
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case TIOCE_ATE_M40S:
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/*
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* ate3240 entries 0-31 are dedicated to port1 super-page
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* mappings. ate3240 entries 32-63 are dedicated to port2.
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*/
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first = port * 32;
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entries = 32;
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ate_shadow = ce_kern->ce_ate3240_shadow;
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ate_reg = ce_mmr->ce_ure_ate3240;
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pagesize = GB(16);
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bus_base = TIOCE_M40S_MIN;
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msi_capable = 0;
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break;
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default:
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return 0;
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}
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msi_wanted = dma_flags & SN_DMA_MSI;
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if (msi_wanted && !msi_capable)
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return 0;
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nates = ATE_NPAGES(ct_addr, len, pagesize);
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if (nates > entries)
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return 0;
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last = first + entries - nates;
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for (i = first; i <= last; i++) {
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if (ATE_VALID(ate_shadow[i]))
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continue;
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for (j = i; j < i + nates; j++)
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if (ATE_VALID(ate_shadow[j]))
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break;
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if (j >= i + nates)
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break;
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}
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if (i > last)
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return 0;
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map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC);
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if (!map)
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return 0;
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addr = ct_addr;
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for (j = 0; j < nates; j++) {
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u64 ate;
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ate = ATE_MAKE(addr, pagesize, msi_wanted);
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ate_shadow[i + j] = ate;
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tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate);
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addr += pagesize;
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}
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map->refcnt = 1;
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map->nbytes = nates * pagesize;
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map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize);
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map->pci_start = bus_base + (i * pagesize);
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map->ate_hw = &ate_reg[i];
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map->ate_shadow = &ate_shadow[i];
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map->ate_count = nates;
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list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list);
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return (map->pci_start + (ct_addr - map->ct_start));
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}
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/**
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* tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
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* @pdev: linux pci_dev representing the function
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* @paddr: system physical address
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*
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* Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
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*/
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static u64
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tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags)
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{
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int dma_ok;
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int port;
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struct tioce __iomem *ce_mmr;
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struct tioce_kernel *ce_kern;
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u64 ct_upper;
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u64 ct_lower;
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dma_addr_t bus_addr;
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if (dma_flags & SN_DMA_MSI)
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return 0;
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ct_upper = ct_addr & ~0x3fffffffUL;
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ct_lower = ct_addr & 0x3fffffffUL;
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pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
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if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
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u64 tmp;
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ce_kern->ce_port[port].dirmap_shadow = ct_upper;
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tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
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ct_upper);
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tmp = ce_mmr->ce_ure_dir_map[port];
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dma_ok = 1;
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} else
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dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper);
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if (dma_ok) {
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ce_kern->ce_port[port].dirmap_refcnt++;
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bus_addr = TIOCE_D32_MIN + ct_lower;
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} else
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bus_addr = 0;
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return bus_addr;
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}
|
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|
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/**
|
|
* tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
|
|
* the barrier bit.
|
|
* @bus_addr: bus address to swizzle
|
|
*
|
|
* Given a TIOCE bus address, set the appropriate bit to indicate barrier
|
|
* attributes.
|
|
*/
|
|
static u64
|
|
tioce_dma_barrier(u64 bus_addr, int on)
|
|
{
|
|
u64 barrier_bit;
|
|
|
|
/* barrier not supported in M40/M40S mode */
|
|
if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
|
|
return bus_addr;
|
|
|
|
if (TIOCE_D64_ADDR(bus_addr))
|
|
barrier_bit = (1UL << 62);
|
|
else /* must be m32 or d32 */
|
|
barrier_bit = (1UL << 30);
|
|
|
|
return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit);
|
|
}
|
|
|
|
/**
|
|
* tioce_dma_unmap - release CE mapping resources
|
|
* @pdev: linux pci_dev representing the function
|
|
* @bus_addr: bus address returned by an earlier tioce_dma_map
|
|
* @dir: mapping direction (unused)
|
|
*
|
|
* Locate mapping resources associated with @bus_addr and release them.
|
|
* For mappings created using the direct modes there are no resources
|
|
* to release.
|
|
*/
|
|
void
|
|
tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
|
|
{
|
|
int i;
|
|
int port;
|
|
struct tioce_kernel *ce_kern;
|
|
struct tioce __iomem *ce_mmr;
|
|
unsigned long flags;
|
|
|
|
bus_addr = tioce_dma_barrier(bus_addr, 0);
|
|
pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
|
|
|
|
/* nothing to do for D64 */
|
|
|
|
if (TIOCE_D64_ADDR(bus_addr))
|
|
return;
|
|
|
|
spin_lock_irqsave(&ce_kern->ce_lock, flags);
|
|
|
|
if (TIOCE_D32_ADDR(bus_addr)) {
|
|
if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
|
|
ce_kern->ce_port[port].dirmap_shadow = 0;
|
|
tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port],
|
|
0);
|
|
}
|
|
} else {
|
|
struct tioce_dmamap *map;
|
|
|
|
list_for_each_entry(map, &ce_kern->ce_dmamap_list,
|
|
ce_dmamap_list) {
|
|
u64 last;
|
|
|
|
last = map->pci_start + map->nbytes - 1;
|
|
if (bus_addr >= map->pci_start && bus_addr <= last)
|
|
break;
|
|
}
|
|
|
|
if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) {
|
|
printk(KERN_WARNING
|
|
"%s: %s - no map found for bus_addr 0x%llx\n",
|
|
__func__, pci_name(pdev), bus_addr);
|
|
} else if (--map->refcnt == 0) {
|
|
for (i = 0; i < map->ate_count; i++) {
|
|
map->ate_shadow[i] = 0;
|
|
tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0);
|
|
}
|
|
|
|
list_del(&map->ce_dmamap_list);
|
|
kfree(map);
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
|
|
}
|
|
|
|
/**
|
|
* tioce_do_dma_map - map pages for PCI DMA
|
|
* @pdev: linux pci_dev representing the function
|
|
* @paddr: host physical address to map
|
|
* @byte_count: bytes to map
|
|
*
|
|
* This is the main wrapper for mapping host physical pages to CE PCI space.
|
|
* The mapping mode used is based on the device's dma_mask.
|
|
*/
|
|
static u64
|
|
tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
|
|
int barrier, int dma_flags)
|
|
{
|
|
unsigned long flags;
|
|
u64 ct_addr;
|
|
u64 mapaddr = 0;
|
|
struct tioce_kernel *ce_kern;
|
|
struct tioce_dmamap *map;
|
|
int port;
|
|
u64 dma_mask;
|
|
|
|
dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
|
|
|
|
/* cards must be able to address at least 31 bits */
|
|
if (dma_mask < 0x7fffffffUL)
|
|
return 0;
|
|
|
|
if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
|
|
ct_addr = PHYS_TO_TIODMA(paddr);
|
|
else
|
|
ct_addr = paddr;
|
|
|
|
/*
|
|
* If the device can generate 64 bit addresses, create a D64 map.
|
|
*/
|
|
if (dma_mask == ~0UL) {
|
|
mapaddr = tioce_dma_d64(ct_addr, dma_flags);
|
|
if (mapaddr)
|
|
goto dma_map_done;
|
|
}
|
|
|
|
pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
|
|
|
|
spin_lock_irqsave(&ce_kern->ce_lock, flags);
|
|
|
|
/*
|
|
* D64 didn't work ... See if we have an existing map that covers
|
|
* this address range. Must account for devices dma_mask here since
|
|
* an existing map might have been done in a mode using more pci
|
|
* address bits than this device can support.
|
|
*/
|
|
list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
|
|
u64 last;
|
|
|
|
last = map->ct_start + map->nbytes - 1;
|
|
if (ct_addr >= map->ct_start &&
|
|
ct_addr + byte_count - 1 <= last &&
|
|
map->pci_start <= dma_mask) {
|
|
map->refcnt++;
|
|
mapaddr = map->pci_start + (ct_addr - map->ct_start);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If we don't have a map yet, and the card can generate 40
|
|
* bit addresses, try the M40/M40S modes. Note these modes do not
|
|
* support a barrier bit, so if we need a consistent map these
|
|
* won't work.
|
|
*/
|
|
if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
|
|
/*
|
|
* We have two options for 40-bit mappings: 16GB "super" ATEs
|
|
* and 64MB "regular" ATEs. We'll try both if needed for a
|
|
* given mapping but which one we try first depends on the
|
|
* size. For requests >64MB, prefer to use a super page with
|
|
* regular as the fallback. Otherwise, try in the reverse order.
|
|
*/
|
|
|
|
if (byte_count > MB(64)) {
|
|
mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
|
|
port, ct_addr, byte_count,
|
|
dma_flags);
|
|
if (!mapaddr)
|
|
mapaddr =
|
|
tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
|
|
ct_addr, byte_count,
|
|
dma_flags);
|
|
} else {
|
|
mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
|
|
ct_addr, byte_count,
|
|
dma_flags);
|
|
if (!mapaddr)
|
|
mapaddr =
|
|
tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
|
|
port, ct_addr, byte_count,
|
|
dma_flags);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* 32-bit direct is the next mode to try
|
|
*/
|
|
if (!mapaddr && dma_mask >= 0xffffffffUL)
|
|
mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags);
|
|
|
|
/*
|
|
* Last resort, try 32-bit ATE-based map.
|
|
*/
|
|
if (!mapaddr)
|
|
mapaddr =
|
|
tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
|
|
byte_count, dma_flags);
|
|
|
|
spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
|
|
|
|
dma_map_done:
|
|
if (mapaddr && barrier)
|
|
mapaddr = tioce_dma_barrier(mapaddr, 1);
|
|
|
|
return mapaddr;
|
|
}
|
|
|
|
/**
|
|
* tioce_dma - standard pci dma map interface
|
|
* @pdev: pci device requesting the map
|
|
* @paddr: system physical address to map into pci space
|
|
* @byte_count: # bytes to map
|
|
*
|
|
* Simply call tioce_do_dma_map() to create a map with the barrier bit clear
|
|
* in the address.
|
|
*/
|
|
static u64
|
|
tioce_dma(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags)
|
|
{
|
|
return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags);
|
|
}
|
|
|
|
/**
|
|
* tioce_dma_consistent - consistent pci dma map interface
|
|
* @pdev: pci device requesting the map
|
|
* @paddr: system physical address to map into pci space
|
|
* @byte_count: # bytes to map
|
|
*
|
|
* Simply call tioce_do_dma_map() to create a map with the barrier bit set
|
|
* in the address.
|
|
*/
|
|
static u64
|
|
tioce_dma_consistent(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags)
|
|
{
|
|
return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags);
|
|
}
|
|
|
|
/**
|
|
* tioce_error_intr_handler - SGI TIO CE error interrupt handler
|
|
* @irq: unused
|
|
* @arg: pointer to tioce_common struct for the given CE
|
|
*
|
|
* Handle a CE error interrupt. Simply a wrapper around a SAL call which
|
|
* defers processing to the SGI prom.
|
|
*/
|
|
static irqreturn_t
|
|
tioce_error_intr_handler(int irq, void *arg)
|
|
{
|
|
struct tioce_common *soft = arg;
|
|
struct ia64_sal_retval ret_stuff;
|
|
ret_stuff.status = 0;
|
|
ret_stuff.v0 = 0;
|
|
|
|
SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
|
|
soft->ce_pcibus.bs_persist_segment,
|
|
soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
|
|
|
|
if (ret_stuff.v0)
|
|
panic("tioce_error_intr_handler: Fatal TIOCE error");
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* tioce_reserve_m32 - reserve M32 ATEs for the indicated address range
|
|
* @tioce_kernel: TIOCE context to reserve ATEs for
|
|
* @base: starting bus address to reserve
|
|
* @limit: last bus address to reserve
|
|
*
|
|
* If base/limit falls within the range of bus space mapped through the
|
|
* M32 space, reserve the resources corresponding to the range.
|
|
*/
|
|
static void
|
|
tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
|
|
{
|
|
int ate_index, last_ate, ps;
|
|
struct tioce __iomem *ce_mmr;
|
|
|
|
ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
|
|
ps = ce_kern->ce_ate3240_pagesize;
|
|
ate_index = ATE_PAGE(base, ps);
|
|
last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
|
|
|
|
if (ate_index < 64)
|
|
ate_index = 64;
|
|
|
|
if (last_ate >= TIOCE_NUM_M3240_ATES)
|
|
last_ate = TIOCE_NUM_M3240_ATES - 1;
|
|
|
|
while (ate_index <= last_ate) {
|
|
u64 ate;
|
|
|
|
ate = ATE_MAKE(0xdeadbeef, ps, 0);
|
|
ce_kern->ce_ate3240_shadow[ate_index] = ate;
|
|
tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index],
|
|
ate);
|
|
ate_index++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* tioce_kern_init - init kernel structures related to a given TIOCE
|
|
* @tioce_common: ptr to a cached tioce_common struct that originated in prom
|
|
*/
|
|
static struct tioce_kernel *
|
|
tioce_kern_init(struct tioce_common *tioce_common)
|
|
{
|
|
int i;
|
|
int ps;
|
|
int dev;
|
|
u32 tmp;
|
|
unsigned int seg, bus;
|
|
struct tioce __iomem *tioce_mmr;
|
|
struct tioce_kernel *tioce_kern;
|
|
|
|
tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
|
|
if (!tioce_kern) {
|
|
return NULL;
|
|
}
|
|
|
|
tioce_kern->ce_common = tioce_common;
|
|
spin_lock_init(&tioce_kern->ce_lock);
|
|
INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
|
|
tioce_common->ce_kernel_private = (u64) tioce_kern;
|
|
|
|
/*
|
|
* Determine the secondary bus number of the port2 logical PPB.
|
|
* This is used to decide whether a given pci device resides on
|
|
* port1 or port2. Note: We don't have enough plumbing set up
|
|
* here to use pci_read_config_xxx() so use raw_pci_read().
|
|
*/
|
|
|
|
seg = tioce_common->ce_pcibus.bs_persist_segment;
|
|
bus = tioce_common->ce_pcibus.bs_persist_busnum;
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
|
|
tioce_kern->ce_port1_secondary = (u8) tmp;
|
|
|
|
/*
|
|
* Set PMU pagesize to the largest size available, and zero out
|
|
* the ATEs.
|
|
*/
|
|
|
|
tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
|
|
tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
|
|
CE_URE_PAGESIZE_MASK);
|
|
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
|
|
CE_URE_256K_PAGESIZE);
|
|
ps = tioce_kern->ce_ate3240_pagesize = KB(256);
|
|
|
|
for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
|
|
tioce_kern->ce_ate40_shadow[i] = 0;
|
|
tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0);
|
|
}
|
|
|
|
for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
|
|
tioce_kern->ce_ate3240_shadow[i] = 0;
|
|
tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0);
|
|
}
|
|
|
|
/*
|
|
* Reserve ATEs corresponding to reserved address ranges. These
|
|
* include:
|
|
*
|
|
* Memory space covered by each PPB mem base/limit register
|
|
* Memory space covered by each PPB prefetch base/limit register
|
|
*
|
|
* These bus ranges are for pio (downstream) traffic only, and so
|
|
* cannot be used for DMA.
|
|
*/
|
|
|
|
for (dev = 1; dev <= 2; dev++) {
|
|
u64 base, limit;
|
|
|
|
/* mem base/limit */
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_MEMORY_BASE, 2, &tmp);
|
|
base = (u64)tmp << 16;
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_MEMORY_LIMIT, 2, &tmp);
|
|
limit = (u64)tmp << 16;
|
|
limit |= 0xfffffUL;
|
|
|
|
if (base < limit)
|
|
tioce_reserve_m32(tioce_kern, base, limit);
|
|
|
|
/*
|
|
* prefetch mem base/limit. The tioce ppb's have 64-bit
|
|
* decoders, so read the upper portions w/o checking the
|
|
* attributes.
|
|
*/
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_PREF_MEMORY_BASE, 2, &tmp);
|
|
base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_PREF_BASE_UPPER32, 4, &tmp);
|
|
base |= (u64)tmp << 32;
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_PREF_MEMORY_LIMIT, 2, &tmp);
|
|
|
|
limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
|
|
limit |= 0xfffffUL;
|
|
|
|
raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
|
|
PCI_PREF_LIMIT_UPPER32, 4, &tmp);
|
|
limit |= (u64)tmp << 32;
|
|
|
|
if ((base < limit) && TIOCE_M32_ADDR(base))
|
|
tioce_reserve_m32(tioce_kern, base, limit);
|
|
}
|
|
|
|
return tioce_kern;
|
|
}
|
|
|
|
/**
|
|
* tioce_force_interrupt - implement altix force_interrupt() backend for CE
|
|
* @sn_irq_info: sn asic irq that we need an interrupt generated for
|
|
*
|
|
* Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to
|
|
* force a secondary interrupt to be generated. This is to work around an
|
|
* asic issue where there is a small window of opportunity for a legacy device
|
|
* interrupt to be lost.
|
|
*/
|
|
static void
|
|
tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
|
|
{
|
|
struct pcidev_info *pcidev_info;
|
|
struct tioce_common *ce_common;
|
|
struct tioce_kernel *ce_kern;
|
|
struct tioce __iomem *ce_mmr;
|
|
u64 force_int_val;
|
|
|
|
if (!sn_irq_info->irq_bridge)
|
|
return;
|
|
|
|
if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE)
|
|
return;
|
|
|
|
pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
|
|
if (!pcidev_info)
|
|
return;
|
|
|
|
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
|
|
ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
|
|
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
|
|
|
|
/*
|
|
* TIOCE Rev A workaround (PV 945826), force an interrupt by writing
|
|
* the TIO_INTx register directly (1/26/2006)
|
|
*/
|
|
if (ce_common->ce_rev == TIOCE_REV_A) {
|
|
u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit);
|
|
u64 status;
|
|
|
|
tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status);
|
|
if (status & int_bit_mask) {
|
|
u64 force_irq = (1 << 8) | sn_irq_info->irq_irq;
|
|
u64 ctalk = sn_irq_info->irq_xtalkaddr;
|
|
u64 nasid, offset;
|
|
|
|
nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT;
|
|
offset = (ctalk & CTALK_NODE_OFFSET);
|
|
HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* irq_int_bit is originally set up by prom, and holds the interrupt
|
|
* bit shift (not mask) as defined by the bit definitions in the
|
|
* ce_adm_int mmr. These shifts are not the same for the
|
|
* ce_adm_force_int register, so do an explicit mapping here to make
|
|
* things clearer.
|
|
*/
|
|
|
|
switch (sn_irq_info->irq_int_bit) {
|
|
case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT;
|
|
break;
|
|
case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT:
|
|
force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val);
|
|
}
|
|
|
|
/**
|
|
* tioce_target_interrupt - implement set_irq_affinity for tioce resident
|
|
* functions. Note: only applies to line interrupts, not MSI's.
|
|
*
|
|
* @sn_irq_info: SN IRQ context
|
|
*
|
|
* Given an sn_irq_info, set the associated CE device's interrupt destination
|
|
* register. Since the interrupt destination registers are on a per-ce-slot
|
|
* basis, this will retarget line interrupts for all functions downstream of
|
|
* the slot.
|
|
*/
|
|
static void
|
|
tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
|
|
{
|
|
struct pcidev_info *pcidev_info;
|
|
struct tioce_common *ce_common;
|
|
struct tioce_kernel *ce_kern;
|
|
struct tioce __iomem *ce_mmr;
|
|
int bit;
|
|
u64 vector;
|
|
|
|
pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
|
|
if (!pcidev_info)
|
|
return;
|
|
|
|
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
|
|
ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
|
|
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
|
|
|
|
bit = sn_irq_info->irq_int_bit;
|
|
|
|
tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
|
|
vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
|
|
vector |= sn_irq_info->irq_xtalkaddr;
|
|
tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector);
|
|
tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit));
|
|
|
|
tioce_force_interrupt(sn_irq_info);
|
|
}
|
|
|
|
/**
|
|
* tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
|
|
* @prom_bussoft: Common prom/kernel struct representing the bus
|
|
*
|
|
* Replicates the tioce_common pointed to by @prom_bussoft in kernel
|
|
* space. Allocates and initializes a kernel-only area for a given CE,
|
|
* and sets up an irq for handling CE error interrupts.
|
|
*
|
|
* On successful setup, returns the kernel version of tioce_common back to
|
|
* the caller.
|
|
*/
|
|
static void *
|
|
tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
|
|
{
|
|
struct tioce_common *tioce_common;
|
|
struct tioce_kernel *tioce_kern;
|
|
struct tioce __iomem *tioce_mmr;
|
|
|
|
/*
|
|
* Allocate kernel bus soft and copy from prom.
|
|
*/
|
|
|
|
tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL);
|
|
if (!tioce_common)
|
|
return NULL;
|
|
|
|
memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
|
|
tioce_common->ce_pcibus.bs_base = (unsigned long)
|
|
ioremap(REGION_OFFSET(tioce_common->ce_pcibus.bs_base),
|
|
sizeof(struct tioce_common));
|
|
|
|
tioce_kern = tioce_kern_init(tioce_common);
|
|
if (tioce_kern == NULL) {
|
|
kfree(tioce_common);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Clear out any transient errors before registering the error
|
|
* interrupt handler.
|
|
*/
|
|
|
|
tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
|
|
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
|
|
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
|
|
~0ULL);
|
|
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, 0ULL);
|
|
|
|
if (request_irq(SGI_PCIASIC_ERROR,
|
|
tioce_error_intr_handler,
|
|
IRQF_SHARED, "TIOCE error", (void *)tioce_common))
|
|
printk(KERN_WARNING
|
|
"%s: Unable to get irq %d. "
|
|
"Error interrupts won't be routed for "
|
|
"TIOCE bus %04x:%02x\n",
|
|
__func__, SGI_PCIASIC_ERROR,
|
|
tioce_common->ce_pcibus.bs_persist_segment,
|
|
tioce_common->ce_pcibus.bs_persist_busnum);
|
|
|
|
sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
|
|
return tioce_common;
|
|
}
|
|
|
|
static struct sn_pcibus_provider tioce_pci_interfaces = {
|
|
.dma_map = tioce_dma,
|
|
.dma_map_consistent = tioce_dma_consistent,
|
|
.dma_unmap = tioce_dma_unmap,
|
|
.bus_fixup = tioce_bus_fixup,
|
|
.force_interrupt = tioce_force_interrupt,
|
|
.target_interrupt = tioce_target_interrupt
|
|
};
|
|
|
|
/**
|
|
* tioce_init_provider - init SN PCI provider ops for TIO CE
|
|
*/
|
|
int
|
|
tioce_init_provider(void)
|
|
{
|
|
sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces;
|
|
return 0;
|
|
}
|