746e8d3b22
No-one seems to know how to mask individual baboon interrupts, so we just mask the umbrella IRQ. This will work as long as only the IDE driver uses the baboon chip (it can't deadlock). Use mac_enable_irq/mac_disable_irq rather than enable_irq/disable_irq because the latter routines count the depth of nested calls which triggers a warning and call trace because IRQ_NUBUS_C is enabled twice in a row (once when the baboon handler is registered, and once when the IDE IRQ is registered). Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
513 lines
12 KiB
C
513 lines
12 KiB
C
/*
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* Macintosh interrupts
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*
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* General design:
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* In contrary to the Amiga and Atari platforms, the Mac hardware seems to
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* exclusively use the autovector interrupts (the 'generic level0-level7'
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* interrupts with exception vectors 0x19-0x1f). The following interrupt levels
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* are used:
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* 1 - VIA1
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* - slot 0: one second interrupt (CA2)
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* - slot 1: VBlank (CA1)
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* - slot 2: ADB data ready (SR full)
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* - slot 3: ADB data (CB2)
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* - slot 4: ADB clock (CB1)
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* - slot 5: timer 2
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* - slot 6: timer 1
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* - slot 7: status of IRQ; signals 'any enabled int.'
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*
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* 2 - VIA2 or RBV
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* - slot 0: SCSI DRQ (CA2)
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* - slot 1: NUBUS IRQ (CA1) need to read port A to find which
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* - slot 2: /EXP IRQ (only on IIci)
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* - slot 3: SCSI IRQ (CB2)
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* - slot 4: ASC IRQ (CB1)
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* - slot 5: timer 2 (not on IIci)
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* - slot 6: timer 1 (not on IIci)
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* - slot 7: status of IRQ; signals 'any enabled int.'
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*
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* 2 - OSS (IIfx only?)
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* - slot 0: SCSI interrupt
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* - slot 1: Sound interrupt
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*
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* Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
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*
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* 3 - unused (?)
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*
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* 4 - SCC (slot number determined by reading RR3 on the SSC itself)
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* - slot 1: SCC channel A
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* - slot 2: SCC channel B
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*
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* 5 - unused (?)
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* [serial errors or special conditions seem to raise level 6
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* interrupts on some models (LC4xx?)]
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*
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* 6 - off switch (?)
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*
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* For OSS Macintoshes (IIfx only at this point):
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*
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* 3 - Nubus interrupt
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* - slot 0: Slot $9
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* - slot 1: Slot $A
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* - slot 2: Slot $B
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* - slot 3: Slot $C
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* - slot 4: Slot $D
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* - slot 5: Slot $E
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*
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* 4 - SCC IOP
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* - slot 1: SCC channel A
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* - slot 2: SCC channel B
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*
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* 5 - ISM IOP (ADB?)
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*
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* 6 - unused
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*
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* For PSC Macintoshes (660AV, 840AV):
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*
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* 3 - PSC level 3
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* - slot 0: MACE
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*
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* 4 - PSC level 4
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* - slot 1: SCC channel A interrupt
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* - slot 2: SCC channel B interrupt
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* - slot 3: MACE DMA
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*
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* 5 - PSC level 5
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*
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* 6 - PSC level 6
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*
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* Finally we have good 'ole level 7, the non-maskable interrupt:
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*
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* 7 - NMI (programmer's switch on the back of some Macs)
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* Also RAM parity error on models which support it (IIc, IIfx?)
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*
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* The current interrupt logic looks something like this:
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*
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* - We install dispatchers for the autovector interrupts (1-7). These
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* dispatchers are responsible for querying the hardware (the
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* VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
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* this information a machspec interrupt number is generated by placing the
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* index of the interrupt hardware into the low three bits and the original
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* autovector interrupt number in the upper 5 bits. The handlers for the
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* resulting machspec interrupt are then called.
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*
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* - Nubus is a special case because its interrupts are hidden behind two
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* layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
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* which translates to IRQ number 17. In this spot we install _another_
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* dispatcher. This dispatcher finds the interrupting slot number (9-F) and
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* then forms a new machspec interrupt number as above with the slot number
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* minus 9 in the low three bits and the pseudo-level 7 in the upper five
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* bits. The handlers for this new machspec interrupt number are then
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* called. This puts Nubus interrupts into the range 56-62.
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*
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* - The Baboon interrupts (used on some PowerBooks) are an even more special
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* case. They're hidden behind the Nubus slot $C interrupt thus adding a
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* third layer of indirection. Why oh why did the Apple engineers do that?
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*
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* - We support "fast" and "slow" handlers, just like the Amiga port. The
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* fast handlers are called first and with all interrupts disabled. They
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* are expected to execute quickly (hence the name). The slow handlers are
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* called last with interrupts enabled and the interrupt level restored.
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* They must therefore be reentrant.
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*
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* TODO:
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/interrupt.h> /* for intr_count */
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/bootinfo.h>
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#include <asm/macintosh.h>
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#include <asm/mac_via.h>
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#include <asm/mac_psc.h>
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#include <asm/hwtest.h>
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#include <asm/errno.h>
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#include <asm/macints.h>
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#include <asm/irq_regs.h>
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#define DEBUG_SPURIOUS
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#define SHUTUP_SONIC
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/* SCC interrupt mask */
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static int scc_mask;
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/*
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* VIA/RBV hooks
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*/
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extern void via_init(void);
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extern void via_register_interrupts(void);
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extern void via_irq_enable(int);
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extern void via_irq_disable(int);
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extern void via_irq_clear(int);
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extern int via_irq_pending(int);
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/*
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* OSS hooks
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*/
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extern int oss_present;
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extern void oss_init(void);
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extern void oss_register_interrupts(void);
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extern void oss_irq_enable(int);
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extern void oss_irq_disable(int);
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extern void oss_irq_clear(int);
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extern int oss_irq_pending(int);
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/*
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* PSC hooks
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*/
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extern int psc_present;
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extern void psc_init(void);
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extern void psc_register_interrupts(void);
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extern void psc_irq_enable(int);
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extern void psc_irq_disable(int);
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extern void psc_irq_clear(int);
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extern int psc_irq_pending(int);
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/*
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* IOP hooks
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*/
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extern void iop_register_interrupts(void);
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/*
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* Baboon hooks
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*/
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extern int baboon_present;
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extern void baboon_init(void);
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extern void baboon_register_interrupts(void);
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extern void baboon_irq_enable(int);
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extern void baboon_irq_disable(int);
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extern void baboon_irq_clear(int);
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extern int baboon_irq_pending(int);
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/*
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* SCC interrupt routines
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*/
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static void scc_irq_enable(unsigned int);
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static void scc_irq_disable(unsigned int);
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/*
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* console_loglevel determines NMI handler function
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*/
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irqreturn_t mac_nmi_handler(int, void *);
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irqreturn_t mac_debug_handler(int, void *);
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/* #define DEBUG_MACINTS */
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void mac_enable_irq(unsigned int irq);
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void mac_disable_irq(unsigned int irq);
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static struct irq_controller mac_irq_controller = {
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.name = "mac",
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.lock = __SPIN_LOCK_UNLOCKED(mac_irq_controller.lock),
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.enable = mac_enable_irq,
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.disable = mac_disable_irq,
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};
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void __init mac_init_IRQ(void)
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{
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#ifdef DEBUG_MACINTS
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printk("mac_init_IRQ(): Setting things up...\n");
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#endif
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scc_mask = 0;
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m68k_setup_irq_controller(&mac_irq_controller, IRQ_USER,
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NUM_MAC_SOURCES - IRQ_USER);
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/* Make sure the SONIC interrupt is cleared or things get ugly */
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#ifdef SHUTUP_SONIC
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printk("Killing onboard sonic... ");
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/* This address should hopefully be mapped already */
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if (hwreg_present((void*)(0x50f0a000))) {
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*(long *)(0x50f0a014) = 0x7fffL;
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*(long *)(0x50f0a010) = 0L;
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}
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printk("Done.\n");
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#endif /* SHUTUP_SONIC */
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/*
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* Now register the handlers for the master IRQ handlers
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* at levels 1-7. Most of the work is done elsewhere.
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*/
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if (oss_present)
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oss_register_interrupts();
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else
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via_register_interrupts();
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if (psc_present)
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psc_register_interrupts();
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if (baboon_present)
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baboon_register_interrupts();
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iop_register_interrupts();
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request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
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mac_nmi_handler);
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#ifdef DEBUG_MACINTS
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printk("mac_init_IRQ(): Done!\n");
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#endif
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}
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/*
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* mac_enable_irq - enable an interrupt source
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* mac_disable_irq - disable an interrupt source
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* mac_clear_irq - clears a pending interrupt
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* mac_pending_irq - Returns the pending status of an IRQ (nonzero = pending)
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*
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* These routines are just dispatchers to the VIA/OSS/PSC routines.
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*/
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void mac_enable_irq(unsigned int irq)
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{
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int irq_src = IRQ_SRC(irq);
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switch(irq_src) {
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case 1:
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via_irq_enable(irq);
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break;
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case 2:
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case 7:
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if (oss_present)
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oss_irq_enable(irq);
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else
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via_irq_enable(irq);
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break;
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case 3:
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case 4:
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case 5:
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case 6:
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if (psc_present)
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psc_irq_enable(irq);
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else if (oss_present)
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oss_irq_enable(irq);
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else if (irq_src == 4)
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scc_irq_enable(irq);
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break;
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case 8:
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if (baboon_present)
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baboon_irq_enable(irq);
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break;
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}
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}
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void mac_disable_irq(unsigned int irq)
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{
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int irq_src = IRQ_SRC(irq);
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switch(irq_src) {
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case 1:
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via_irq_disable(irq);
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break;
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case 2:
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case 7:
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if (oss_present)
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oss_irq_disable(irq);
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else
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via_irq_disable(irq);
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break;
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case 3:
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case 4:
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case 5:
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case 6:
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if (psc_present)
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psc_irq_disable(irq);
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else if (oss_present)
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oss_irq_disable(irq);
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else if (irq_src == 4)
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scc_irq_disable(irq);
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break;
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case 8:
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if (baboon_present)
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baboon_irq_disable(irq);
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break;
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}
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}
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void mac_clear_irq(unsigned int irq)
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{
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switch(IRQ_SRC(irq)) {
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case 1:
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via_irq_clear(irq);
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break;
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case 2:
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case 7:
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if (oss_present)
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oss_irq_clear(irq);
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else
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via_irq_clear(irq);
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break;
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case 3:
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case 4:
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case 5:
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case 6:
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if (psc_present)
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psc_irq_clear(irq);
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else if (oss_present)
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oss_irq_clear(irq);
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break;
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case 8:
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if (baboon_present)
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baboon_irq_clear(irq);
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break;
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}
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}
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int mac_irq_pending(unsigned int irq)
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{
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switch(IRQ_SRC(irq)) {
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case 1:
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return via_irq_pending(irq);
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case 2:
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case 7:
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if (oss_present)
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return oss_irq_pending(irq);
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else
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return via_irq_pending(irq);
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case 3:
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case 4:
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case 5:
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case 6:
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if (psc_present)
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return psc_irq_pending(irq);
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else if (oss_present)
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return oss_irq_pending(irq);
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}
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return 0;
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}
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EXPORT_SYMBOL(mac_irq_pending);
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static int num_debug[8];
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irqreturn_t mac_debug_handler(int irq, void *dev_id)
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{
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if (num_debug[irq] < 10) {
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printk("DEBUG: Unexpected IRQ %d\n", irq);
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num_debug[irq]++;
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}
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return IRQ_HANDLED;
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}
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static int in_nmi;
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static volatile int nmi_hold;
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irqreturn_t mac_nmi_handler(int irq, void *dev_id)
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{
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int i;
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/*
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* generate debug output on NMI switch if 'debug' kernel option given
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* (only works with Penguin!)
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*/
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in_nmi++;
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for (i=0; i<100; i++)
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udelay(1000);
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if (in_nmi == 1) {
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nmi_hold = 1;
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printk("... pausing, press NMI to resume ...");
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} else {
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printk(" ok!\n");
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nmi_hold = 0;
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}
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barrier();
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while (nmi_hold == 1)
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udelay(1000);
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if (console_loglevel >= 8) {
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#if 0
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struct pt_regs *fp = get_irq_regs();
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show_state();
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printk("PC: %08lx\nSR: %04x SP: %p\n", fp->pc, fp->sr, fp);
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printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
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fp->d0, fp->d1, fp->d2, fp->d3);
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printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
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fp->d4, fp->d5, fp->a0, fp->a1);
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if (STACK_MAGIC != *(unsigned long *)current->kernel_stack_page)
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printk("Corrupted stack page\n");
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printk("Process %s (pid: %d, stackpage=%08lx)\n",
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current->comm, current->pid, current->kernel_stack_page);
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if (intr_count == 1)
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dump_stack((struct frame *)fp);
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#else
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/* printk("NMI "); */
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#endif
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}
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in_nmi--;
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return IRQ_HANDLED;
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}
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/*
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* Simple routines for masking and unmasking
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* SCC interrupts in cases where this can't be
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* done in hardware (only the PSC can do that.)
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*/
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static void scc_irq_enable(unsigned int irq)
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{
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int irq_idx = IRQ_IDX(irq);
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scc_mask |= (1 << irq_idx);
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}
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static void scc_irq_disable(unsigned int irq)
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{
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int irq_idx = IRQ_IDX(irq);
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scc_mask &= ~(1 << irq_idx);
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}
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/*
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* SCC master interrupt handler. We have to do a bit of magic here
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* to figure out what channel gave us the interrupt; putting this
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* here is cleaner than hacking it into drivers/char/macserial.c.
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*/
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void mac_scc_dispatch(int irq, void *dev_id)
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{
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volatile unsigned char *scc = (unsigned char *) mac_bi_data.sccbase + 2;
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unsigned char reg;
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unsigned long flags;
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/* Read RR3 from the chip. Always do this on channel A */
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/* This must be an atomic operation so disable irqs. */
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local_irq_save(flags);
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*scc = 3;
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reg = *scc;
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local_irq_restore(flags);
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/* Now dispatch. Bits 0-2 are for channel B and */
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/* bits 3-5 are for channel A. We can safely */
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/* ignore the remaining bits here. */
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/* */
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/* Note that we're ignoring scc_mask for now. */
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/* If we actually mask the ints then we tend to */
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/* get hammered by very persistent SCC irqs, */
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/* and since they're autovector interrupts they */
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/* pretty much kill the system. */
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if (reg & 0x38)
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m68k_handle_int(IRQ_SCCA);
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if (reg & 0x07)
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m68k_handle_int(IRQ_SCCB);
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}
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