11eef455c2
This moves the SCC (Super Companion Chip) related code for celleb into platforms/cell/. All files in this patch are used by celleb-beat and celleb-native commonly. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/*
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* SCC (Super Companion Chip) UHC setup
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include "celleb_scc.h"
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#define UHC_RESET_WAIT_MAX 10000
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static inline int uhc_clkctrl_ready(u32 val)
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{
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const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
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return((val & mask) == mask);
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}
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/*
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* UHC(usb host controller) enable function.
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* affect to both of OHCI and EHCI core module.
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*/
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static void enable_scc_uhc(struct pci_dev *dev)
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{
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void __iomem *uhc_base;
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u32 __iomem *uhc_clkctrl;
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u32 __iomem *uhc_ecmode;
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u32 val = 0;
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int i;
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if (!machine_is(celleb_beat) &&
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!machine_is(celleb_native))
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return;
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uhc_base = ioremap(pci_resource_start(dev, 0),
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pci_resource_len(dev, 0));
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if (!uhc_base) {
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printk(KERN_ERR "failed to map UHC register base.\n");
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return;
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}
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uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
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uhc_ecmode = uhc_base + SCC_UHC_ECMODE;
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/* setup for normal mode */
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val |= SCC_UHC_F48MCKLEN;
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out_be32(uhc_clkctrl, val);
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val |= SCC_UHC_PHY_SUSPEND_SEL;
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out_be32(uhc_clkctrl, val);
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udelay(10);
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val |= SCC_UHC_PHYEN;
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out_be32(uhc_clkctrl, val);
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udelay(50);
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/* disable reset */
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val |= SCC_UHC_HCLKEN;
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out_be32(uhc_clkctrl, val);
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val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
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out_be32(uhc_clkctrl, val);
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i = 0;
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while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
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udelay(10);
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if (i++ > UHC_RESET_WAIT_MAX) {
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printk(KERN_ERR "Failed to disable UHC reset %x\n",
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in_be32(uhc_clkctrl));
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break;
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}
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}
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/* Endian Conversion Mode for Master ALL area */
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out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
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iounmap(uhc_base);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
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PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);
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