7f9ce7143e
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
89 lines
2.1 KiB
Text
89 lines
2.1 KiB
Text
/*
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* P2020 DS Device Tree Source
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/p2020si-pre.dtsi"
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/ {
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model = "fsl,P2020DS";
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compatible = "fsl,P2020DS";
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@ffe05000 {
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ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
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0x1 0x0 0x0 0xe0000000 0x08000000
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0x2 0x0 0x0 0xffa00000 0x00040000
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0x3 0x0 0x0 0xffdf0000 0x00008000
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0x4 0x0 0x0 0xffa40000 0x00040000
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0x5 0x0 0x0 0xffa80000 0x00040000
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0x6 0x0 0x0 0xffac0000 0x00040000>;
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reg = <0 0xffe05000 0 0x1000>;
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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};
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pci2: pcie@ffe08000 {
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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reg = <0 0xffe08000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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board_pci1: pci1: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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reg = <0 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci0: pcie@ffe0a000 {
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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reg = <0 0xffe0a000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/*
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* p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
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* for interrupt-map & interrupt-map-mask
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*/
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/include/ "fsl/p2020si-post.dtsi"
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/include/ "p2020ds.dtsi"
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