a26be149fa
This time with:
* Generic page-table framework for ARM IOMMUs using the LPAE page-table
format, ARM-SMMU and Renesas IPMMU make use of it already.
* Break out of the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The first
user will be the ARM64 common DMA-API implementation for IOMMUs
* Device tree support for Renesas IPMMU
* Various fixes and cleanups all over the place
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJU3MJOAAoJECvwRC2XARrjopUP+wachFx8vb00M4hlnlwL6FCn
DyIFkA1n4wL0muPhjcBI+LViEXrSxjr2TYoJEaBg+fiByWWQ1Hefg+KPz331Lo1D
+uo7WiOa1AB3pfkQiUN9IN6xx+o6ivhb3UQPiL4FHjggB/qz+KVxMM9nx0j8o0fQ
D9q6HLFiOIsFkra3xZaSuDGvYUBpcwyfn8FP1HVfvLlg1uxIGDcUJX3qU5UBpj9q
al/lPZ4A7rp+JLApV6WyouPiyVOZKikb5x920KeRNBem7a9fNBdgf+x7QbKpNXa1
5MaT5MarwGe8lJE4wtjOqRtsllhia+A1rg/6JbROPrlGetRFiuIh2sCKLvwOCko/
IjBHSutpaRT1lFoAG0TAnXQlvHRG/58XxOlP3eF613X/p8/cezuUaTyTIwZam9X3
j2GWwbUcBiHTxlu7bQDPz6a7cTf4w6wEALzYl18QrAFv+2LqlCfOo/LSlpStmjrF
kRN8DYaohlTULvmFneSr8rfGsnp5yPgIPvdmqiSwTz/Ih7kYPgfLy6+v6IAHUqZj
0n9oGs8eMqVvSzM2qqmyA9WGuQZRyhNjj4iDwn/he5YMw2kqxUQYGMpLnSu0Oi48
n4PqodtVol64jKLwaHZwyU8u71iyjUC5K9TDot/I2wlSRcTELJhxGh6c1sfDLyrO
u/htIszgKCgFvVrQoEZB
=dwrA
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
"This time with:
- Generic page-table framework for ARM IOMMUs using the LPAE
page-table format, ARM-SMMU and Renesas IPMMU make use of it
already.
- Break out the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The
first user will be the ARM64 common DMA-API implementation for
IOMMUs
- Device tree support for Renesas IPMMU
- Various fixes and cleanups all over the place"
* tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (36 commits)
iommu/amd: Convert non-returned local variable to boolean when relevant
iommu: Update my email address
iommu/amd: Use wait_event in put_pasid_state_wait
iommu/amd: Fix amd_iommu_free_device()
iommu/arm-smmu: Avoid build warning
iommu/fsl: Various cleanups
iommu/fsl: Use %pa to print phys_addr_t
iommu/omap: Print phys_addr_t using %pa
iommu: Make more drivers depend on COMPILE_TEST
iommu/ipmmu-vmsa: Fix IOMMU lookup when multiple IOMMUs are registered
iommu: Disable on !MMU builds
iommu/fsl: Remove unused fsl_of_pamu_ids[]
iommu/fsl: Fix section mismatch
iommu/ipmmu-vmsa: Use the ARM LPAE page table allocator
iommu: Fix trace_map() to report original iova and original size
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
iopoll: Introduce memory-mapped IO polling macros
iommu/arm-smmu: don't touch the secure STLBIALL register
iommu/arm-smmu: make use of generic LPAE allocator
iommu: io-pgtable-arm: add non-secure quirk
...
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
|
|
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
|
* Author: Joerg Roedel <jroedel@suse.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published
|
|
* by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
*
|
|
* This header file contains stuff that is shared between different interrupt
|
|
* remapping drivers but with no need to be visible outside of the IOMMU layer.
|
|
*/
|
|
|
|
#ifndef __IRQ_REMAPPING_H
|
|
#define __IRQ_REMAPPING_H
|
|
|
|
#ifdef CONFIG_IRQ_REMAP
|
|
|
|
struct IO_APIC_route_entry;
|
|
struct io_apic_irq_attr;
|
|
struct irq_data;
|
|
struct cpumask;
|
|
struct pci_dev;
|
|
struct msi_msg;
|
|
|
|
extern int irq_remap_broken;
|
|
extern int disable_sourceid_checking;
|
|
extern int no_x2apic_optout;
|
|
extern int irq_remapping_enabled;
|
|
|
|
struct irq_remap_ops {
|
|
/* Initializes hardware and makes it ready for remapping interrupts */
|
|
int (*prepare)(void);
|
|
|
|
/* Enables the remapping hardware */
|
|
int (*enable)(void);
|
|
|
|
/* Disables the remapping hardware */
|
|
void (*disable)(void);
|
|
|
|
/* Reenables the remapping hardware */
|
|
int (*reenable)(int);
|
|
|
|
/* Enable fault handling */
|
|
int (*enable_faulting)(void);
|
|
|
|
/* IO-APIC setup routine */
|
|
int (*setup_ioapic_entry)(int irq, struct IO_APIC_route_entry *,
|
|
unsigned int, int,
|
|
struct io_apic_irq_attr *);
|
|
|
|
/* Set the CPU affinity of a remapped interrupt */
|
|
int (*set_affinity)(struct irq_data *data, const struct cpumask *mask,
|
|
bool force);
|
|
|
|
/* Free an IRQ */
|
|
int (*free_irq)(int);
|
|
|
|
/* Create MSI msg to use for interrupt remapping */
|
|
void (*compose_msi_msg)(struct pci_dev *,
|
|
unsigned int, unsigned int,
|
|
struct msi_msg *, u8);
|
|
|
|
/* Allocate remapping resources for MSI */
|
|
int (*msi_alloc_irq)(struct pci_dev *, int, int);
|
|
|
|
/* Setup the remapped MSI irq */
|
|
int (*msi_setup_irq)(struct pci_dev *, unsigned int, int, int);
|
|
|
|
/* Setup interrupt remapping for an HPET MSI */
|
|
int (*alloc_hpet_msi)(unsigned int, unsigned int);
|
|
};
|
|
|
|
extern struct irq_remap_ops intel_irq_remap_ops;
|
|
extern struct irq_remap_ops amd_iommu_irq_ops;
|
|
|
|
#else /* CONFIG_IRQ_REMAP */
|
|
|
|
#define irq_remapping_enabled 0
|
|
#define irq_remap_broken 0
|
|
|
|
#endif /* CONFIG_IRQ_REMAP */
|
|
|
|
#endif /* __IRQ_REMAPPING_H */
|