9cb0d1babf
Patchc08e20d"arm: Add v7_invalidate_l1 to cache-v7.S" added a generic version of this function and removed all platform specific versions, while4898de3"ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures" added another one, leading to a link error. I verified that the two are identical, so we can just remove the one in mach-prima2. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
40 lines
1,007 B
ArmAsm
40 lines
1,007 B
ArmAsm
/*
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* Entry of the second core for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__CPUINIT
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/*
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* SIRFSOC specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(sirfsoc_secondary_startup)
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(sirfsoc_secondary_startup)
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.align
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1: .long .
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.long pen_release
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