d7e7e4ffc6
Add INTC_IRQ_PINS_16H to allow broken out support of the the high 16 external interrupt pins. On SoCs with 32 external interrupt pins the interrupt vectors for the low 16 and the high 16 interrupt pins are sparesly populated. The low 16 are at 0x0200 and high 16 are at 0x3200 which with current macros results in a separation of 384 linux interrupts. This sparse population makes it unsuitable with a single IRQ domain to cover the full IRQ range, so this macro breaks out the 32 pins into two separate 16 bit controllers to allow two independent INTC instances with two separate IRQ domains. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
290 lines
10 KiB
C
290 lines
10 KiB
C
#ifndef __ASM_MACH_INTC_H
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#define __ASM_MACH_INTC_H
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#include <linux/sh_intc.h>
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#define INTC_IRQ_PINS_ENUM_16L(p) \
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p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
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p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \
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p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
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p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15
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#define INTC_IRQ_PINS_ENUM_16H(p) \
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p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
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p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \
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p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
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p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31
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#define INTC_IRQ_PINS_VECT_16L(p, vect) \
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vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \
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vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \
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vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \
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vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \
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vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \
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vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \
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vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \
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vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0)
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#define INTC_IRQ_PINS_VECT_16H(p, vect) \
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vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \
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vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \
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vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \
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vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \
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vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \
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vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \
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vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \
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vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0)
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#define INTC_IRQ_PINS_MASK_16L(p, base) \
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{ base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \
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{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
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p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
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{ base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \
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{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
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p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
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#define INTC_IRQ_PINS_MASK_16H(p, base) \
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{ base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \
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{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
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p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
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{ base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \
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{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
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p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
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#define INTC_IRQ_PINS_PRIO_16L(p, base) \
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{ base + 0x10, 0, 32, 4, /* INTPRI00A */ \
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{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
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p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
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{ base + 0x14, 0, 32, 4, /* INTPRI10A */ \
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{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
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p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
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#define INTC_IRQ_PINS_PRIO_16H(p, base) \
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{ base + 0x18, 0, 32, 4, /* INTPRI20A */ \
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{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
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p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
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{ base + 0x1c, 0, 32, 4, /* INTPRI30A */ \
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{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
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p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
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#define INTC_IRQ_PINS_SENSE_16L(p, base) \
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{ base + 0x00, 32, 4, /* ICR1A */ \
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{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
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p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
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{ base + 0x04, 32, 4, /* ICR2A */ \
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{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
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p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
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#define INTC_IRQ_PINS_SENSE_16H(p, base) \
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{ base + 0x08, 32, 4, /* ICR3A */ \
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{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
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p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
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{ base + 0x0c, 32, 4, /* ICR4A */ \
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{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
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p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
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#define INTC_IRQ_PINS_ACK_16L(p, base) \
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{ base + 0x20, 0, 8, /* INTREQ00A */ \
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{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
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p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
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{ base + 0x24, 0, 8, /* INTREQ10A */ \
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{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
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p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
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#define INTC_IRQ_PINS_ACK_16H(p, base) \
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{ base + 0x28, 0, 8, /* INTREQ20A */ \
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{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
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p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
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{ base + 0x2c, 0, 8, /* INTREQ30A */ \
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{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
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p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
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#define INTC_IRQ_PINS_16(p, base, vect, str) \
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\
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static struct resource p ## _resources[] __initdata = { \
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[0] = { \
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.start = base, \
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.end = base + 0x64, \
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.flags = IORESOURCE_MEM, \
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}, \
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}; \
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\
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enum { \
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p ## _UNUSED = 0, \
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INTC_IRQ_PINS_ENUM_16L(p), \
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}; \
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\
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static struct intc_vect p ## _vectors[] __initdata = { \
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INTC_IRQ_PINS_VECT_16L(p, vect), \
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}; \
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\
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static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
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INTC_IRQ_PINS_MASK_16L(p, base), \
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}; \
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\
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static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
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INTC_IRQ_PINS_PRIO_16L(p, base), \
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}; \
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\
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static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
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INTC_IRQ_PINS_SENSE_16L(p, base), \
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}; \
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\
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static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
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INTC_IRQ_PINS_ACK_16L(p, base), \
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}; \
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\
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static struct intc_desc p ## _desc __initdata = { \
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.name = str, \
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.resource = p ## _resources, \
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.num_resources = ARRAY_SIZE(p ## _resources), \
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.hw = INTC_HW_DESC(p ## _vectors, NULL, \
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p ## _mask_registers, p ## _prio_registers, \
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p ## _sense_registers, p ## _ack_registers) \
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}
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#define INTC_IRQ_PINS_16H(p, base, vect, str) \
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\
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static struct resource p ## _resources[] __initdata = { \
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[0] = { \
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.start = base, \
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.end = base + 0x64, \
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.flags = IORESOURCE_MEM, \
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}, \
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}; \
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\
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enum { \
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p ## _UNUSED = 0, \
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INTC_IRQ_PINS_ENUM_16H(p), \
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}; \
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\
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static struct intc_vect p ## _vectors[] __initdata = { \
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INTC_IRQ_PINS_VECT_16H(p, vect), \
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}; \
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\
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static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
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INTC_IRQ_PINS_MASK_16H(p, base), \
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}; \
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\
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static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
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INTC_IRQ_PINS_PRIO_16H(p, base), \
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}; \
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\
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static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
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INTC_IRQ_PINS_SENSE_16H(p, base), \
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}; \
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\
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static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
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INTC_IRQ_PINS_ACK_16H(p, base), \
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}; \
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\
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static struct intc_desc p ## _desc __initdata = { \
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.name = str, \
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.resource = p ## _resources, \
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.num_resources = ARRAY_SIZE(p ## _resources), \
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.hw = INTC_HW_DESC(p ## _vectors, NULL, \
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p ## _mask_registers, p ## _prio_registers, \
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p ## _sense_registers, p ## _ack_registers) \
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}
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#define INTC_IRQ_PINS_32(p, base, vect, str) \
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\
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static struct resource p ## _resources[] __initdata = { \
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[0] = { \
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.start = base, \
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.end = base + 0x6c, \
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.flags = IORESOURCE_MEM, \
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}, \
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}; \
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\
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enum { \
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p ## _UNUSED = 0, \
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INTC_IRQ_PINS_ENUM_16L(p), \
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INTC_IRQ_PINS_ENUM_16H(p), \
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}; \
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\
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static struct intc_vect p ## _vectors[] __initdata = { \
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INTC_IRQ_PINS_VECT_16L(p, vect), \
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INTC_IRQ_PINS_VECT_16H(p, vect), \
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}; \
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\
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static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
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INTC_IRQ_PINS_MASK_16L(p, base), \
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INTC_IRQ_PINS_MASK_16H(p, base), \
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}; \
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\
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static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
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INTC_IRQ_PINS_PRIO_16L(p, base), \
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INTC_IRQ_PINS_PRIO_16H(p, base), \
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}; \
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\
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static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
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INTC_IRQ_PINS_SENSE_16L(p, base), \
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INTC_IRQ_PINS_SENSE_16H(p, base), \
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}; \
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\
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static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
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INTC_IRQ_PINS_ACK_16L(p, base), \
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INTC_IRQ_PINS_ACK_16H(p, base), \
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}; \
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\
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static struct intc_desc p ## _desc __initdata = { \
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.name = str, \
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.resource = p ## _resources, \
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.num_resources = ARRAY_SIZE(p ## _resources), \
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.hw = INTC_HW_DESC(p ## _vectors, NULL, \
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p ## _mask_registers, p ## _prio_registers, \
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p ## _sense_registers, p ## _ack_registers) \
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}
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#define INTC_PINT_E_EMPTY
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#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
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#define INTC_PINT_E(p) \
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PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
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PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
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#define INTC_PINT_V_NONE
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#define INTC_PINT_V(p, vect) \
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vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \
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vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \
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vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \
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vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
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#define INTC_PINT(p, mask_reg, sense_base, str, \
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enums_1, enums_2, enums_3, enums_4, \
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vect_1, vect_2, vect_3, vect_4, \
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mask_a, mask_b, mask_c, mask_d, \
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sense_a, sense_b, sense_c, sense_d) \
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\
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enum { \
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PINT ## p ## _UNUSED = 0, \
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enums_1 enums_2 enums_3 enums_4 \
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}; \
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\
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static struct intc_vect p ## _vectors[] __initdata = { \
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vect_1 vect_2 vect_3 vect_4 \
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}; \
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\
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static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
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{ mask_reg, 0, 32, /* PINTER */ \
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{ mask_a mask_b mask_c mask_d } } \
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}; \
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\
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static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
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{ sense_base + 0x00, 16, 2, /* PINTCR */ \
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{ sense_a } }, \
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{ sense_base + 0x04, 16, 2, /* PINTCR */ \
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{ sense_b } }, \
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{ sense_base + 0x08, 16, 2, /* PINTCR */ \
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{ sense_c } }, \
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{ sense_base + 0x0c, 16, 2, /* PINTCR */ \
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{ sense_d } }, \
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}; \
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\
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static struct intc_desc p ## _desc __initdata = { \
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.name = str, \
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.hw = INTC_HW_DESC(p ## _vectors, NULL, \
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p ## _mask_registers, NULL, \
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p ## _sense_registers, NULL), \
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}
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#endif /* __ASM_MACH_INTC_H */
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