a11b18ef94
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
106 lines
3.2 KiB
C
106 lines
3.2 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Defines of the MIPS boards specific address-MAP, registers, etc.
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*/
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#ifndef __ASM_MIPS_BOARDS_GENERIC_H
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#define __ASM_MIPS_BOARDS_GENERIC_H
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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#include <asm/mips-boards/bonito64.h>
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/*
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* Display register base.
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*/
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#ifdef CONFIG_MIPS_SEAD
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#define ASCII_DISPLAY_POS_BASE 0x1f0005c0
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#else
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#define ASCII_DISPLAY_WORD_BASE 0x1f000410
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#define ASCII_DISPLAY_POS_BASE 0x1f000418
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#endif
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/*
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* Yamon Prom print address.
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*/
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#define YAMON_PROM_PRINT_ADDR 0x1fc00504
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/*
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* Reset register.
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*/
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#ifdef CONFIG_MIPS_SEAD
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#define SOFTRES_REG 0x1e800050
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#define GORESET 0x4d
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#else
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#define SOFTRES_REG 0x1f000500
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#define GORESET 0x42
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#endif
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/*
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* Revision register.
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*/
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#define MIPS_REVISION_REG 0x1fc00010
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#define MIPS_REVISION_CORID_QED_RM5261 0
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#define MIPS_REVISION_CORID_CORE_LV 1
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#define MIPS_REVISION_CORID_BONITO64 2
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#define MIPS_REVISION_CORID_CORE_20K 3
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#define MIPS_REVISION_CORID_CORE_FPGA 4
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#define MIPS_REVISION_CORID_CORE_MSC 5
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#define MIPS_REVISION_CORID_CORE_EMUL 6
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#define MIPS_REVISION_CORID_CORE_FPGA2 7
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#define MIPS_REVISION_CORID_CORE_FPGAR2 8
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#define MIPS_REVISION_CORID_CORE_FPGA3 9
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#define MIPS_REVISION_CORID_CORE_24K 10
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#define MIPS_REVISION_CORID_CORE_FPGA4 11
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/**** Artificial corid defines ****/
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/*
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* CoreEMUL with Bonito System Controller is treated like a Core20K
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* CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
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*/
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#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
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#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
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#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
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extern int mips_revision_corid;
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#define MIPS_REVISION_SCON_OTHER 0
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#define MIPS_REVISION_SCON_SOCITSC 1
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#define MIPS_REVISION_SCON_SOCITSCP 2
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/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
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#define MIPS_REVISION_SCON_UNKNOWN -1
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#define MIPS_REVISION_SCON_GT64120 -2
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#define MIPS_REVISION_SCON_BONITO -3
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#define MIPS_REVISION_SCON_BRTL -4
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#define MIPS_REVISION_SCON_SOCIT -5
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#define MIPS_REVISION_SCON_ROCIT -6
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#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
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extern int mips_revision_sconid;
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#ifdef CONFIG_PCI
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extern void mips_pcibios_init(void);
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#else
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#define mips_pcibios_init() do { } while (0)
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#endif
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#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
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