7cc1c4b2c4
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
97 lines
4.4 KiB
C
97 lines
4.4 KiB
C
/*
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* File: include/asm-blackfin/mach-bf548/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* False Hardware Error Exception when ISR context is not restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
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/* TWI Slave Boot Mode Is Not Functional */
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#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
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/* External FIFO Boot Mode Is Not Functional */
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#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
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/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
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#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
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/* Synchronous Burst Flash Boot Mode Is Not Functional */
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#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
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/* Host DMA Boot Mode Is Not Functional */
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
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#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
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/* Inadequate Rotary Debounce Logic Duration */
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#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
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/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
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#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
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/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
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#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
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/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
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#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
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/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
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#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
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/* USB Calibration Value Is Not Intialized */
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#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
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/* Data Lost when Core Reads SDH Data FIFO */
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#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
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/* PLL Status Register Is Inaccurate */
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#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* External Memory Read Access Hangs Core With PLL Bypass */
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#define ANOMALY_05000360 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000365 (1)
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/* Addressing Conflict between Boot ROM and Asynchronous Memory */
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#define ANOMALY_05000369 (1)
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/* Mobile DDR Operation Not Functional */
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#define ANOMALY_05000377 (1)
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
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#define ANOMALY_05000378 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#endif
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