02bfc030e4
Connect the omap_hwmod code to the kernel boot. Create some basic interconnect and device structures for OMAP2/3 chips. Signed-off-by: Paul Walmsley <paul@pwsan.com>
168 lines
4.5 KiB
C
168 lines
4.5 KiB
C
/*
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* omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips
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*
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* Copyright (C) 2009 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
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#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
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#ifdef CONFIG_ARCH_OMAP34XX
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#include <mach/omap_hwmod.h>
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#include <mach/irqs.h>
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#include <mach/cpu.h>
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#include <mach/dma.h>
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#include "prm-regbits-34xx.h"
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static struct omap_hwmod omap34xx_mpu_hwmod;
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static struct omap_hwmod omap34xx_l3_hwmod;
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static struct omap_hwmod omap34xx_l4_core_hwmod;
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static struct omap_hwmod omap34xx_l4_per_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = {
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.master = &omap34xx_l3_hwmod,
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.slave = &omap34xx_l4_core_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L3 -> L4_PER interface */
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static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = {
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.master = &omap34xx_l3_hwmod,
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.slave = &omap34xx_l4_per_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* MPU -> L3 interface */
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static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = {
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.master = &omap34xx_mpu_hwmod,
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.slave = &omap34xx_l3_hwmod,
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.user = OCP_USER_MPU,
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};
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/* Slave interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = {
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&omap34xx_mpu__l3,
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};
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/* Master interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = {
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&omap34xx_l3__l4_core,
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&omap34xx_l3__l4_per,
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};
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/* L3 */
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static struct omap_hwmod omap34xx_l3_hwmod = {
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.name = "l3_hwmod",
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.masters = omap34xx_l3_masters,
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.masters_cnt = ARRAY_SIZE(omap34xx_l3_masters),
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.slaves = omap34xx_l3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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static struct omap_hwmod omap34xx_l4_wkup_hwmod;
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/* L4_CORE -> L4_WKUP interface */
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static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = {
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.master = &omap34xx_l4_core_hwmod,
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.slave = &omap34xx_l4_wkup_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* Slave interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = {
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&omap34xx_l3__l4_core,
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};
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/* Master interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = {
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&omap34xx_l4_core__l4_wkup,
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};
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/* L4 CORE */
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static struct omap_hwmod omap34xx_l4_core_hwmod = {
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.name = "l4_core_hwmod",
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.masters = omap34xx_l4_core_masters,
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.masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters),
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.slaves = omap34xx_l4_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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/* Slave interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = {
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&omap34xx_l3__l4_per,
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};
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/* Master interfaces on the L4_PER interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = {
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};
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/* L4 PER */
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static struct omap_hwmod omap34xx_l4_per_hwmod = {
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.name = "l4_per_hwmod",
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.masters = omap34xx_l4_per_masters,
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.masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters),
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.slaves = omap34xx_l4_per_slaves,
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.slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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/* Slave interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = {
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&omap34xx_l4_core__l4_wkup,
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};
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/* Master interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = {
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};
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/* L4 WKUP */
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static struct omap_hwmod omap34xx_l4_wkup_hwmod = {
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.name = "l4_wkup_hwmod",
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.masters = omap34xx_l4_wkup_masters,
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.masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters),
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.slaves = omap34xx_l4_wkup_slaves,
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.slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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/* Master interfaces on the MPU device */
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static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = {
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&omap34xx_mpu__l3,
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};
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/* MPU */
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static struct omap_hwmod omap34xx_mpu_hwmod = {
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.name = "mpu_hwmod",
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.clkdev_dev_id = NULL,
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.clkdev_con_id = "arm_fck",
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.masters = omap34xx_mpu_masters,
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.masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
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&omap34xx_l3_hwmod,
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&omap34xx_l4_core_hwmod,
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&omap34xx_l4_per_hwmod,
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&omap34xx_l4_wkup_hwmod,
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&omap34xx_mpu_hwmod,
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NULL,
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};
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#else
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# define omap34xx_hwmods 0
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#endif
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#endif
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