433a9389a1
Some ARM versions of Chromebook need to download a new calibration data from host driver to firmware. They do have EEPROM but still need a piece of new calibration data in test mode. The cal-data is platform dependent. It's simpler and more feasible to use device tree based cal-data instead of configuration file based cal-data. This patch remove configuration file based cal-data downloading and replace it using cal-data from device tree. When CONFIG_OF is not selected, or the specific property is not present in the device tree, the calibration downloading will not happen. Cc: Mike Frysinger <vapier@chromium.org> Cc: Amitkumar Karwar <akarwar@marvell.com> Signed-off-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Hyuckjoo Lee <hyuckjoo.lee@samsung.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
112 lines
3 KiB
C
112 lines
3 KiB
C
/**
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* Marvell BT-over-SDIO driver: SDIO interface related definitions
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*
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* Copyright (C) 2009, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*
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**/
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#define SDIO_HEADER_LEN 4
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/* SD block size can not bigger than 64 due to buf size limit in firmware */
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/* define SD block size for data Tx/Rx */
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#define SDIO_BLOCK_SIZE 64
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/* Number of blocks for firmware transfer */
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#define FIRMWARE_TRANSFER_NBLOCK 2
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/* This is for firmware specific length */
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#define FW_EXTRA_LEN 36
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#define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
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#define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
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(HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
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#define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
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MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
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+ SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
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* SDIO_BLOCK_SIZE)
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/* The number of times to try when polling for status */
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#define MAX_POLL_TRIES 100
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/* Max retry number of CMD53 write */
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#define MAX_WRITE_IOMEM_RETRY 2
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/* register bitmasks */
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#define HOST_POWER_UP BIT(1)
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#define HOST_CMD53_FIN BIT(2)
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#define HIM_DISABLE 0xff
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#define HIM_ENABLE (BIT(0) | BIT(1))
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#define UP_LD_HOST_INT_STATUS BIT(0)
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#define DN_LD_HOST_INT_STATUS BIT(1)
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#define DN_LD_CARD_RDY BIT(0)
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#define CARD_IO_READY BIT(3)
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#define FIRMWARE_READY 0xfedc
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struct btmrvl_sdio_card_reg {
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u8 cfg;
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u8 host_int_mask;
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u8 host_intstatus;
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u8 card_status;
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u8 sq_read_base_addr_a0;
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u8 sq_read_base_addr_a1;
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u8 card_revision;
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u8 card_fw_status0;
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u8 card_fw_status1;
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u8 card_rx_len;
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u8 card_rx_unit;
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u8 io_port_0;
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u8 io_port_1;
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u8 io_port_2;
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};
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struct btmrvl_sdio_card {
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struct sdio_func *func;
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u32 ioport;
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const char *helper;
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const char *firmware;
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const struct btmrvl_sdio_card_reg *reg;
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u16 sd_blksz_fw_dl;
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u8 rx_unit;
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struct btmrvl_private *priv;
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};
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struct btmrvl_sdio_device {
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const char *helper;
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const char *firmware;
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const struct btmrvl_sdio_card_reg *reg;
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u16 sd_blksz_fw_dl;
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};
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/* Platform specific DMA alignment */
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#define BTSDIO_DMA_ALIGN 8
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/* Macros for Data Alignment : size */
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#define ALIGN_SZ(p, a) \
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(((p) + ((a) - 1)) & ~((a) - 1))
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/* Macros for Data Alignment : address */
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#define ALIGN_ADDR(p, a) \
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((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
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~(((unsigned long)(a)) - 1))
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