Jim Quinlan 71ca758889 MIPS: Make local_irq_disable macro safe for non-Mipsr2 ... For non-mipsr2 processors, the local_irq_disable contains an mfc0-mtc0 pair with instructions inbetween. With preemption enabled, this sequence may get preempted and effect a stale value of CP0_STATUS when executing the mtc0 instruction. This commit avoids this scenario by incrementing the preempt count before the mfc0 and decrementing it after the mtc9. [ralf@linux-mips.org: This patch is sorting out the part that were missed by e97c5b6098 [MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus.] I also re-enabled the inclusion of <asm/asm-offsets.h> at the top of <asm/asmmacro.h>]. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-03-20 13:46:15 +01:00
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asm	MIPS: Make local_irq_disable macro safe for non-Mipsr2	2014-03-20 13:46:15 +01:00
uapi/asm	MIPS: math-emu: Fix prefx detection and COP1X function field definition	2014-03-11 23:10:55 +01:00