dcc1dd2366
Rewrite the SN pio_phys_xxx macros in assembly language. This avoids issues with the Intel icc compiler. Function call overhead is not an issue - the functions reference PIOs and take 100's nsec to complete. In addition, the functions should likely be in assembly language anyway - they reference memory using physical addressing mode. One function executes with psr.ic disabled. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
28 lines
944 B
C
28 lines
944 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
|
|
*/
|
|
#ifndef _ASM_IA64_SN_RW_MMR_H
|
|
#define _ASM_IA64_SN_RW_MMR_H
|
|
|
|
|
|
/*
|
|
* This file that access MMRs via uncached physical addresses.
|
|
* pio_phys_read_mmr - read an MMR
|
|
* pio_phys_write_mmr - write an MMR
|
|
* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
|
|
* Second MMR will be skipped if address is NULL
|
|
*
|
|
* Addresses passed to these routines should be uncached physical addresses
|
|
* ie., 0x80000....
|
|
*/
|
|
|
|
|
|
extern long pio_phys_read_mmr(volatile long *mmr);
|
|
extern void pio_phys_write_mmr(volatile long *mmr, long val);
|
|
extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
|
|
|
|
#endif /* _ASM_IA64_SN_RW_MMR_H */
|